Datasheet

REV. –6–
AD7226
INTERFACE LOGIC INFORMATION
Address lines A0 and A1 select which DAC will accept data
from the input port. Table I shows the selection table for the
four DACs with Figure 4 showing the input control logic. When
the WR signal is LOW, the input latches of the selected DAC
are transparent and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of WR. While WR is high the analog outputs remain
at the value corresponding to the data held in their respective latches.
Table I. AD7226 Truth Table
AD7226 Control Inputs AD7226
WR A1 A0 Operation
HXXNo Operation Device Not Selected
LLLDAC A Transparent
LLDAC A Latched
LLHDAC B Transparent
LHDAC B Latched
LHLDAC C Transparent
HLDAC C Latched
LHHDAC D Transparent
HHDAC D Latched
L = Low State, H = High State, X = Don’t Care
A0
A1
W
R
TO LATCH A
TO LATCH B
TO LATCH C
TO LATCH D
Figure 4. Input Control Logic
t
DS
t
DH
t
AH
t
AS
V
INL
V
INH
V
INH
V
INL
V
DD
V
DD
V
DD
DATA
ADDRESS
WR
0
0
0
t
WR
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES
MEASURED FROM 10% TO 90% OF V
DD
.
t
r
= t
f
= 20ns OVER V
DD
RANGE.
2. TIMING MEASUREMENT REFERENCE LEVEL IS
3. SELECTED INPUT LATCH IS TRANSPARENT WHILE WR IS
LOW, THUS INVALID DATA DURING THIS TIME CAN CAUSE
SPURIOUS OUTPUTS.
V
INH
+ V
INL
2
Figure 5. Write Cycle Timing Diagram
D