Datasheet
AD7225
Rev. C | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
OUT
B
1
V
OUT
A
2
V
SS
3
V
REF
B
4
V
OUT
C
24
V
OUT
D
23
V
DD
22
V
REF
C
21
V
REF
A
5
V
REF
D
20
AGND
6
A0
19
DGND
7
A1
18
LDAC
8
WR
17
DB7
9
DB0
16
DB6
10
DB1
15
DB5
11
DB2
14
DB4
12
DB3
13
AD7225
TOP VIEW
(Not to Scale)
00986-002
1 28 27 26234
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC = NO CONNECT
V
REF
B
V
REF
A
AGND
NC
DGND
LDAC
DB7
V
REF
C
V
REF
D
A0
NC
A1
WR
DB0
V
SS
V
OUT
A
V
OUT
B
NC
V
OUT
C
V
OUT
D
V
DD
DB6
DB5
DB4
NC
DB3
DB2
DB1
PIN 1
INDENTFIER
12 13 14 15 16 17 18
AD7225
TOP VIEW
(Not to Scale)
00986-003
Figure 2. PDIP, SOIC, CERDIP, and SSOP Figure 3. PLCC
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
PDIP, SOIC,
CERDIP, SSOP
PLCC
1 2 V
OUT
B DAC Channel B Voltage Output.
2 3 V
OUT
A DAC Channel A Voltage Output.
3 4 V
SS
Negative Power Supply Connection.
4 5 V
REF
B Reference Voltage Connection for DAC Channel B.
5 6 V
REF
A Reference Voltage Connection for DAC Channel A.
6 7 AGND Analog Ground Reference Connection.
7 9 DGND Digital Ground Reference Connection.
8 10
LDAC Active Low Load DAC Signal. DAC register data is latched on the rising edge of LDAC.
9 11 DB7 Data Bit 7 (Most Significant Data Bit).
10 12 DB6 Data Bit 6.
11 13 DB5 Data Bit 5.
12 14 DB4 Data Bit 4.
13 16 DB3 Data Bit 3.
14 17 DB2 Data Bit 2.
15 18 DB1 Data Bit 1.
16 19 DB0 Data Bit 0 (Least Significant Data Bit).
17 20
WR Active Low Data Write Signal. Input register data is latched on the rising edge of WR.
18 21 A1 DAC Address Select Pin.
19 23 A0 DAC Address Select Pin.
20 24 V
REF
D Reference Voltage Connection for DAC Channel D.
21 25 V
REF
C Reference Voltage Connection for DAC Channel C.
22 26 V
DD
Positive Power Supply Connection.
23 27 V
OUT
D DAC Channel D Voltage Output.
24 28 V
OUT
C DAC Channel C Voltage Output.
N/A 1, 8, 15, 22 NC No Internal Connection.