Datasheet

AD7225
Rev. C | Page 15 of 24
AGND BIAS
The AD7225 AGND pin can be biased above system ground
(AD7225 DGND) to provide an offset zero analog output
voltage level. Figure 18 shows a circuit configuration to achieve
this for DAC Channel A of the AD7225. The output voltage,
V
OUT
A, can be expressed as:
V
OUT
A = V
BIAS
+ D
A
(V
IN
)
where D
A
is a fractional representation of the digital word in
DAC Latch A (0 ≤ D
A
≤ 255/256).
V
DD
V
SS
AGND
V
BIAS
V
IN
DGND
V
OUT
A
DAC A
AD7225*
V
REF
A
*DIGITAL INPUTS OMITTED FOR CLARITY.
00986-018
Figure 18. AGND Bias Circuit
For a given V
IN
, increasing AGND above system ground reduces
the effective V
DD
− V
REF
, which must be at least 4 V to ensure
specified operation. Note that, because the AGND pin is
common to all four DACs, this method biases up the output
voltages of all the DACs in the AD7225. Note that V
DD
and V
SS
of the AD7225 should be referenced to DGND.