Datasheet

AD7225
Rev. C | Page 10 of 24
INTERFACE LOGIC INFORMATION
The AD7225 contains two registers per DAC, an input register
and a DAC register. The A0 and A1 address lines select which
input register accepts data from the input port. When the
WR
signal is low, the input latches of the selected DAC are transpa-
rent. The data is latched into the addressed input register on the
rising edge of Table 5
WR
. shows the addressing for the input
registers on the AD7225.
Table 5. AD7225 Addressing
A1 A0 Selected Input Register
Low Low DAC A
Low High DAC B
High Low DAC C
High High DAC D
Only the data held in the DAC register determines the analog
output of the converter. The
LDAC
signal is common to all four
DACs and controls the transfer of information from the input
registers to the DAC registers. Data is latched into all four DAC
registers simultaneously on the rising edge of
LDAC
. The
LDAC
signal is level triggered and therefore the DAC registers can be
made transparent by tying
LDAC
low (in this case, the outputs
of the converters respond to the data held in their respective
input latches).
LDAC
is an asynchronous signal and is indepen-
dent of
WR
. This is useful in many applications. However, in
systems where the asynchronous
LDAC
can occur during a
write cycle (or vice versa), care must be taken to ensure that
incorrect data is not latched through to the output. If
LDAC
is
activated prior to the rising edge of
WR
(or
WR
occurs during
LDAC
),
LDAC
must stay low for t
6
or longer after
WR
Table 6. Truth Table
goes high
to ensure correct data is latched through to the output. Table 6
shows the truth table for AD7225 operation. Figure 12 shows
the input control logic for the part; the write cycle timing
diagram is given in Figure 13.
WR LDAC
Function
High High No operation. Device not selected.
Low High Input register of selected DAC transparent.
High Input register of selected DAC latched.
High Low
All four DAC registers Transparent (that is,
outputs respond to data held in respective
input registers). Input registers are latched.
High All four DAC registers latched.
Low Low
DAC registers and selected input register
transparent output follows input data for
selected channel.
TO INPUT
LATCH A
TO INPUT
LATCH B
TO ALL
DAC LATCHES
TO INPUT
LATCH C
TO INPUT
LATCH D
LDAC
A0
A1
WR
00986-012
Figure 12. Input Control Logic
ADDRESS
DATA IN
LDAC
WR
5V
5V
5V
0V
5V
0V
DATA
VALID
V
INH
V
INL
t
2
t
3
t
1
t
6
t
5
t
4
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM
10% TO 90% OF 5V.
t
R
=
t
F
= 20ns OVER V
DD
RANGE.
2. TIMING MEASUREMENT REFERENCE LEVEL IS
3. IF LDAC IS ACTIVATED PRIOR TO THE RISING EDGE OF WR,
THEN IT MUST STAY LOW FOR
t
6
OR LONGER AFTER WR
GOES HIGH.
V
INH
+ V
INL
2
00986-013
Figure 13. Write Cycle Timing Diagram