Datasheet

AD7195
Rev. 0 | Page 5 of 44
Parameter Min Typ Max Unit Test Conditions/Comments
1
LOGIC INPUTS
Input High Voltage, V
INH
2
2 V
Input Low Voltage, V
INL
2
0.8 V
Hysteresis
2
0.1 0.25 V
Input Currents −10 +10 μA
LOGIC OUTPUT (DOUT/
RDY
)
Output High Voltage, V
OH
2
DV
DD
− 0.6 V DV
DD
= 3 V, I
SOURCE
= 100 μA
Output Low Voltage, V
OL
2
0.4 V DV
DD
= 3 V, I
SINK
= 100 μA
Output High Voltage, V
OH
2
4 V DV
DD
= 5 V, I
SOURCE
= 200 μA
Output Low Voltage, V
OL
2
0.4 V DV
DD
= 5 V, I
SINK
= 1.6 mA
Floating-State Leakage
Current
−10 +10 μA
Floating-State Output
Capacitance
10 pF
Data Output Coding Offset binary
SYSTEM CALIBRATION
2
Full-Scale Calibration Limit 1.05 × FS V
Zero-Scale Calibration Limit −1.05 × FS V
Input Span 0.8 × FS 2.1 × FS V
POWER REQUIREMENTS
7
Power Supply Voltage
AV
DD
− AGND 4.75 5.25 V
DV
DD
− DGND 2.7 5.25 V
Power Supply Currents
AI
DD
Current 0.85 1 mA gain = 1, buffer off
1.1 1.3 mA gain = 1, buffer on
3.5 4.5 mA gain = 8, buffer off
4 5 mA gain = 8, buffer on
5 6.4 mA gain = 16 to 128, buffer off
5.5 6.9 mA gain = 16 to 128, buffer on
DI
DD
Current 0.35 0.4 mA DV
DD
= 3 V
0.5 0.6 mA DV
DD
= 5 V
1.5 mA External crystal used
I
DD
(Power-Down Mode) 2 μA
1
Temperature range: −40°C to +105°C.
2
Specification is not production tested, but is supported by characterization data at initial product release.
3
FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.
4
Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-
scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
5
The analog inputs are configured for differential mode.
6
REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.
7
Digital inputs equal to DV
DD
or DGND.