Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 24 Bit LFCSP WQ 32

AD7195

Rev. 0 | Page 18 of 44

COMMUNICATIONS REGISTER

(RS2, RS1, RS0 = 0, 0, 0)

The communications register is an 8-bit write-only register.

All communications to the part must start with a write

operation to the communications register. The data written

to the communications register determines whether the next

operation is a read or a write operation and in which register

this operation takes place. For read or write operations, when

the subsequent read or write operation to the selected register

is complete, the interface returns to where it expects a write

operation to the communications register. This is the default

state of the interface and, on power-up or after a reset, the

ADC is in this default state waiting for a write operation to

the communications register. In situations where the interface

sequence is lost, a write operation of at least 40 serial clock

cycles with DIN high returns the ADC to this default state by

resetting the entire part. Table 19 outlines the bit designations

for the communications register. CR0 through CR7 indicate the

bit location, CR denoting that the bits are in the communications

number in parentheses indicates the power-on/reset default

status of that bit.

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

WEN(0) R/W(0)

RS2(0) RS1(0) RS0(0) CREAD(0) 0 0

Table 19. Communications Register Bit Designations

Bit Location Bit Name Description

CR7

WEN

Write enable bit. For a write to the communications register to occur, 0 must be written to this bit. If a 1 is

the first bit written, the part does not clock on to subsequent bits in the register; rather, it stays at this bit

location until a 0 is written to this bit. After a 0 is written to the WEN

bit, the next seven bits are loaded to

the communications register. Idling the DIN pin high between data transfers minimizes the effects of

spurious SCLK pulses on the serial interface.

CR6

R/W

A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position

indicates that the next operation is a read from the designated register.

CR5 to CR3 RS2 to RS0

the serial interface communication (see Table 20).

CR2 CREAD

Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial

interface is configured so that the data register can be continuously read; that is, the contents of the data

goes low to indicate that a conversion is complete. The communications register does not have to be

written to for subsequent data reads. To enable continuous read, the Instruction 01011100 must be written

to the communications register. To disable continuous read, the Instruction 01011000 must be written to

the communications register while the RDY

pin is low. While continuous read is enabled, the ADC monitors

activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset

occurs if 40 consecutive 1s are seen on DIN. Therefore, hold DIN low until an instruction is written to the