Datasheet

Data Sheet AD7194
Rev. A | Page 33 of 56
Single Conversion Mode
In single conversion mode, the AD7194 is placed in power-
down mode after conversions. When a single conversion is
initiated by setting MD2 to 0, MD1 to 0, and MD0 to 1 in the
mode register, the AD7194 powers up, performs a single
conversion, and then returns to power-down mode. The on-
chip oscillator requires 200 µs, approximately, to power up.
DOUT/
RDY
goes low to indicate the completion of a conver-
sion. When the data-word has been read from the data register,
DOUT/
RDY
goes high. If
CS
is low, DOUT/
RDY
remains high
until another conversion is initiated and completed. The data
register can be read several times, if required, even when
DOUT/
RDY
has gone high.
If the DAT_STA bit in the mode register is set to 1, the contents
of the status register are output along with the conversion each
time that the data read is performed. The four LSBs of the status
register indicate the channel to which the conversion corresponds.
DIN
SCLK
DOUT/RDY
CS
0x08 0x58
DATA
0x280060
08566-023
Figure 24. Single Conversion