Datasheet

AD7194 Data Sheet
Rev. A | Page 26 of 56
Channel Selection (Pseudo Bit = 0)
Table 22. Positive Input Selection
Positive Input Enable Bits in
the Configuration Register
Positive
Input Enabled
AIN(+)
Status
Register Bits
CHD[3:0]
CH7 CH6 CH5 CH4
0 0 0 0 AIN1 0000
0 0 0 1 AIN2 0001
0 0 1 0 AIN3 0010
0 0 1 1 AIN4 0011
0 1 0 0 AIN5 0100
0 1 0 1 AIN6 0101
0 1 1 0 AIN7 0110
0 1 1 1 AIN8 0111
1 0 0 0 AIN9 1000
1 0 0 1 AIN10 1001
1 0 1 0 AIN11
1010
1
0
1
1
AIN12
1011
1
1
0
0
AIN13
1100
1
1
0
1
AIN14
1101
1
1
1
0
AIN15
1110
1
1
1
1
AIN16 1111
Table 23. Negative Input Selection
Negative Input Enable Bits in the
Configuration Register
Negative
Input Enabled
AIN(−)
CH3
CH2
CH1
CH0
0 0 0 0 AIN1
0 0 0 1 AIN2
0 0 1 0 AIN3
0 0 1 1 AIN4
0 1 0 0 AIN5
0 1 0 1 AIN6
0 1 1 0 AIN7
0 1 1 1 AIN8
1 0 0 0 AIN9
1 0 0 1 AIN10
1 0 1 0 AIN11
1
0
1
1
AIN12
1
1
0
0
AIN13
1
1
0
1
AIN14
1
1
1
0
AIN15
1
1
1
1
AIN16
Table 24. Channel Selection (Pseudo Bit = 1)
Channel Enable Bits in the Configuration Register Channel Enabled
Status Register
Bits CHD[3:0]
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Positive Input AIN(+) Negative Input AIN(−)
0 0 0 0 X X X X AIN1 AINCOM 0000
0 0 0 1 X X X X AIN2 AINCOM 0001
0 0 1 0 X X X X AIN3 AINCOM 0010
0 0 1 1 X X X X AIN4 AINCOM 0011
0 1 0 0 X X X X AIN5 AINCOM 0100
0 1 0 1 X X X X AIN6 AINCOM 0101
0 1 1 0 X X X X AIN7 AINCOM 0110
0 1 1 1 X X X X AIN8 AINCOM 0111
1 0 0 0 X X X X AIN9 AINCOM 1000
1 0 0 1 X X X X AIN10 AINCOM 1001
1 0 1 0 X X X X AIN11 AINCOM 1010
1 0 1 1 X X X X AIN12 AINCOM 1011
1 1 0 0 X X X X AIN13 AINCOM 1100
1
1
0
1
X
X
X
X
AIN14
AINCOM
1101
1 1 1 0 X X X X AIN15 AINCOM 1110
1 1 1 1 X X X X AIN16 AINCOM 1111