8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA AD7194 Data Sheet FEATURES Pressure measurement Temperature measurement Flow measurement Weigh scales Chromatography Medical and scientific instrumentation Fast settling filter option 8 differential/16 pseudo differential input channels RMS noise: 11 nV at 4.7 Hz (gain = 128) 15.5 noise-free bits at 2.
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AD7194 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Programmable Gain Array (PGA) ........................................... 30 Applications ....................................................................................... 1 Reference ..................................................................................... 30 General Description .................................................................
Data Sheet AD7194 SPECIFICATIONS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = +2.5 V or AVDD, REFINx(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1.
AD7194 Data Sheet Unit Test Conditions/Comments 1 100 dB 74 dB 96 97 dB dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 50 Hz output data rate, REJ60 6 = 1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 50 Hz output data rate, 50 Hz ± 1 Hz 60 Hz output data rate, 60 Hz ± 1 Hz 120 dB 82 dB 120 120 dB dB 75 dB 60 dB 70 70 dB dB 100 dB 67 dB 95 95 dB dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 50 Hz output data rate, REJ606 = 1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 50 Hz output data rate, 50 Hz
Data Sheet Parameter REFERENCE INPUT REFIN Voltage Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift AD7194 Max Unit Test Conditions/Comments 1 1 AVDD V REFIN = REFINx(+) − REFINx(−), the differential input must be limited to ±(AVDD − 1.25 V)/gain when gain > 1 AGND − 0.05 AVDD + 0.
AD7194 Parameter SYSTEM CALIBRATION2 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS 7 Power Supply Voltage AVDD − AGND DVDD − DGND Power Supply Currents AIDD Current DIDD Current IDD Data Sheet Min Typ Max Unit 1.05 × FS V V 0.8 × FS 2.1 × FS V 3 2.7 5.25 5.25 V V 1.1 1.35 3.6 3.85 4.7 5.3 0.4 0.6 mA mA mA mA mA mA mA mA mA µA −1.05 × FS 0.85 1 2.8 3.2 3.8 4.3 0.35 0.5 1.
Data Sheet AD7194 TIMING CHARACTERISTICS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2.
AD7194 Data Sheet Circuit and Timing Diagrams ISINK (1.6mA WITH DVDD = 5V, 100µA WITH DVDD = 3V) TO OUTPUT PIN 1.6V ISOURCE (200µA WITH DVDD = 5V, 100µA WITH DVDD = 3V) 08566-002 50pF Figure 2. Load Circuit for Timing Characterization CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 SCLK (I) 08566-003 t4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev.
Data Sheet AD7194 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to AGND DVDD to AGND AGND to DGND Analog Input Voltage to AGND Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND AINx/Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Temperature, Soldering Reflow Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +0.3 V −0.3 V to AVDD + 0.3 V −0.
AD7194 Data Sheet 32 31 30 29 28 27 26 25 CS SCLK MCLK2 MCLK1 DIN DOUT/RDY NC SYNC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD7194 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 DVDD AVDD DGND AGND AIN16 AIN15 REFIN1(–) REFIN1(+) NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO AGND. 08566-005 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 9 10 11 12 13 14 15 16 AIN1/P3 AIN2/P2 AIN3/P1/REFIN2(+) AIN4/P0/REFIN2(–) AINCOM AGND AIN5 AIN6 Figure 5. Pin Configuration Table 5.
Data Sheet Pin No. 23 Mnemonic AVDD 24 DVDD 25 SYNC 26 27 NC DOUT/RDY 28 DIN 29 MCLK1 30 MCLK2 31 SCLK 32 CS AD7194 Description Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with AVDD at 5 V or vice versa. Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V with DVDD at 5 V or vice versa.
AD7194 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 50 8,387,952 8,387,950 40 8,387,948 OCCURRENCE CODE 8,387,946 8,387,944 8,387,942 8,387,940 30 20 8,387,938 10 8,387,934 200 400 600 1000 800 SAMPLE 0 8,388,830 08566-006 0 8,388,890 8,388,860 8,388,920 CODE Figure 6. Noise (VREF = AVDD = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) 08566-009 8,387,936 Figure 9.
Data Sheet AD7194 5 0.6 4 0.5 OFFSET ERROR (μV) 2 1 0 0.3 0.2 0.1 –1 –3 –2 –1 1 0 3 2 4 VIN (V) 0 –60 08566-012 –2 –4 0.4 –40 –20 0 20 40 60 80 100 120 TEMPERAUTRE (°C) 08566-067 INL (ppm of FSR) 3 Figure 15. Offset vs. Temperature (Gain = 128, Chop Disabled) Figure 12. INL (Gain = 1) 1.000008 20 1.000006 15 1.000004 10 1.000000 GAIN INL (ppm of FSR) 1.000002 5 0 0.999998 0.999996 –5 0.999994 –10 0.999992 –15 0.01 0 0.02 0.03 VIN (V) 0.
AD7194 Data Sheet 23 NOISE FREE RESOLUTION (Bits) 22 20 18 GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128 10 100 1k 10k OUTPUT DATA RATE (Hz) Figure 18. Noise-Free Resolution (Sinc4 Filter, Chop Disabled, VREF = 5 V) 24 20 18 16 GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128 12 10 1 10 100 OUTPUT DATA RATE (Hz) 1k 10k 08566-070 NOISE FREE RESOLUTION (Bits) 22 14 21 20 19 18 17 14 1 GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128 22 Figure 19.
Data Sheet AD7194 RMS NOISE AND RESOLUTION is continuously converting on a single channel. It is important to note that the effective resolution is calculated using the rms noise, whereas the peak-to-peak resolution is calculated based on peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker. With chop enabled, the resolution improves by 0.5 bits.
AD7194 Data Sheet SINC3 CHOP DISABLED Table 9. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 20 10 3.13 1.25 0.
Data Sheet AD7194 FAST SETTLING Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 96 30 6 5 2 1 Average 16 16 16 16 16 16 Output Data Rate (Hz) 2.63 8.4 42.10 50.53 126.32 252.63 Settling Time (ms) 380 118.75 23.75 19.79 7.92 3.96 1 410 700 1500 1600 2700 3700 8 87 140 270 280 380 540 16 52 71 150 160 210 300 Gain of 32 33 43 82 88 130 190 64 15 30 56 61 94 140 128 12 21 47 52 85 120 64 100 190 360 390 580 850 128 70 130 300 330 510 740 64 23.3 (20.6) 22.3 (19.6) 21.
AD7194 Data Sheet ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described on the following pages wherein the term, set, implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. Table 15. Register Summary Register Communications Addr. 00 Dir.
Data Sheet AD7194 COMMUNICATIONS REGISTER RS2, RS1, RS0 = 000 The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determine whether the next operation is a read or write operation and in which register this operation occurs.
AD7194 Data Sheet STATUS REGISTER RS2, RS1, RS0 = 000; Power-On/Reset = 0x80 The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read operation, and SR7 RDY(1) SR6 ERR(0) SR5 NOREF(0) SR4 Parity(0) load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 18 outlines the bit designations for the status register.
Data Sheet AD7194 MODE REGISTER RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060 The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the output data rate, and the clock source. Table 19 outlines the bit designations for the mode MR23 MD2(0) MR15 SINC3(0) MR7 FS7(0) MR22 MD1(0) MR14 0 MR6 FS6(1) MR21 MD0(0) MR13 ENPAR(0) MR5 FS5(1) MR20 DAT_STA(0) MR12 CLK_DIV(0) MR4 FS4(0) register.
AD7194 Data Sheet Bit Location MR12 Bit Name CLK_DIV MR11 Single MR10 REJ60 MR9 to MR0 FS9 to FS0 Description Clock divide-by-2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, set this bit to 0. When performing internal full-scale calibrations, this bit must be set when AVDD is less than 4.75 V. The calibration accuracy is optimized when chop is enabled and a low output data rate is used while performing the calibration. When AVDD is greater than or equal to 4.
Data Sheet AD7194 Table 20. Operating Modes (MD) MD2 0 MD1 0 MD0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mode Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register go low when a conversion is complete.
AD7194 Data Sheet CONFIGURATION REGISTER RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117 The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel.
Data Sheet AD7194 Table 21. Configuration Register Bit Designations Bit Location CON23 Bit Name Chop CON22, CON21 CON20 0 REFSEL CON19 CON18 0 Pseudo CON17 CON16 0 Temp CON16 to CON8 CH7 to CH0 CON7 Burn CON6 REFDET CON5 CON4 0 BUF CON3 U/B CON2 to CON0 G2 to G0 Description Chop enable bit. When the chop bit is cleared, chop is disabled. With chop disabled, higher conversion rates are allowed.
AD7194 Data Sheet Channel Selection (Pseudo Bit = 0) Table 22. Positive Input Selection Positive Input Enable Bits in the Configuration Register CH7 CH6 CH5 CH4 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Positive Input Enabled AIN(+) AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN16 Table 23.
Data Sheet AD7194 GPOCON REGISTER DATA REGISTER RS2, RS1, RS0 = 011; Power-On/Reset = 0x000000 RS2, RS1, RS0 = 101; Power-On/Reset = 0x00 The conversion result from the ADC is stored in this data register. This is a read-only, 24-bit register. Upon completion of a read operation from this register, the RDY pin/bit is set. When the DAT_STA bit in the mode register is set to 1, the contents of the status register are appended to each 24-bit conversion.
AD7194 Data Sheet OFFSET REGISTER FULL-SCALE REGISTER RS2, RS1, RS0 = 110; Power-On/Reset = 0x800000) RS2, RS1, RS0 = 111; Power-On/Reset = 0x5XXXX0 The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The register is a 24-bit read/write register. It is used in conjunction with the full-scale register to form a register pair.
Data Sheet AD7194 ADC CIRCUIT INFORMATION AVDD AGND DGND REFIN1(+) REFIN1(–) REFERENCE DETECT AD7194 AIN1/P3 AIN2/P2 AIN3/P1/REFIN2(+) AIN4/P0/REFIN2(–) AIN5 DVDD VDD MUX Σ-Δ ADC PGA AIN16 SERIAL INTERFACE AND CONTROL LOGIC DOUT/RDY DIN SCLK CS AINCOM AGND MCLK1 MCLK2 08566-021 CLOCK CIRCUITRY TEMP SENSOR Figure 21.
AD7194 Data Sheet ANALOG INPUT CHANNEL The AD7194 uses flexible multiplexing so any of the analog input pins AIN1 to AIN16 can be selected as a positive input or a negative input (see Table 22 and Table 23). The AINCOM pin can be a negative analog input pin only. AVDD AIN1 AVDD PGA When the gain stage is enabled, the output from the buffer is applied to the input of the PGA.
Data Sheet AD7194 impedance. External decoupling on the REFINx pins is not recommended in this type of circuit configuration. Conversely, if large decoupling capacitors are used on the reference inputs, there should be no resistors in series with the reference inputs. Recommended 2.5 V reference voltage sources for the AD7194 include the ADR421 and ADR431, which are low noise references. These references tolerate decoupling capacitors on REFINx(+) without introducing gain errors in the system.
AD7194 Data Sheet DIGITAL INTERFACE As indicated in the On-Chip Registers section, the programmable functions of the AD7194 are controlled using a set of on-chip registers. Data is written to these registers via the serial interface of the part. Read access to the on-chip registers is also provided by this interface. All communication with the part must start with a write to the communications register. After power-on or reset, the device expects a write to its communications register.
Data Sheet AD7194 Single Conversion Mode In single conversion mode, the AD7194 is placed in powerdown mode after conversions. When a single conversion is initiated by setting MD2 to 0, MD1 to 0, and MD0 to 1 in the mode register, the AD7194 powers up, performs a single conversion, and then returns to power-down mode. The onchip oscillator requires 200 µs, approximately, to power up. DOUT/RDY goes low to indicate the completion of a conversion.
AD7194 Data Sheet Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7194 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is completed. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, DOUT/RDY goes high.
Data Sheet AD7194 Continuous Read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion, or if insufficient serial clocks are applied to the AD7194 to read the word, the serial output register is reset when the next conversion is complete, and the new conversion is placed in the output serial register.
AD7194 Data Sheet RESET ENABLE PARITY The circuitry and serial interface of the AD7194 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, whereas all on-chip registers are reset to their default values. When the ENPAR bit in the mode register is set to 1, parity is enabled.
Data Sheet AD7194 Following the one-point calibration, the internal temperature sensor has an accuracy of ±2°C, typically. LOGIC OUTPUTS The AD7194 has four general-purpose digital outputs: P0, P1, P2, and P3. These are enabled using the GP32EN and GP10EN bits in the GPOCON register. The pins can be pulled high or low using the P0DAT to P3DAT bits in the GPOCON register; that is, the value at the pin is determined by the setting of the P0DAT to P3DAT bits.
AD7194 Data Sheet An internal zero-scale calibration, system zero-scale calibration, and system full-scale calibration can be performed at any output data rate. An internal full-scale calibration can be performed at any output data rate for which the filter word, FS[9:0], is divisible by 16, FS[9:0] being the decimal equivalent of the 10-bit word written to Bit FS9 to Bit FS0 in the mode register.
Data Sheet AD7194 DIGITAL FILTER The AD7194 offers a lot of flexibility in the digital filter. The device has five filter options. The device can be operated with a sinc3 or sinc4 filter, chop can be enabled or disabled, and zero latency can be enabled. Finally, an averaging block can be included after the sinc filter, which gives a fast settling mode. The option selected affects the output data rate, settling time, and 50 Hz/60 Hz rejection.
AD7194 Data Sheet When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. When conversions are being performed on a single channel and a step change occurs on the analog input, the ADC continues to output fully settled conversions if the step change is synchronized with the conversion process. If the step change is asynchronous, one conversion is output from the ADC, which is not completely settled (see Figure 30).
Data Sheet AD7194 The output data rate is 50 Hz when zero latency is disabled and 12.5 Hz when zero latency is enabled. Figure 34 shows the frequency response of the sinc4 filter. The filter provides 50 Hz ±1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, assuming a stable 4.92 MHz master clock. f3dB = 0.272 × fADC Table 30 gives some examples of FS settings and the corresponding output data rates and settling times. Table 30.
AD7194 Data Sheet The output data rate equals Sinc3 50 Hz/60 Hz Rejection fADC = 1/tSETTLE = fCLK/(3 × 1024 × FS[9:0]) Figure 39 show the frequency response of the sinc3 filter when FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The output data rate is equal to 50 Hz when zero latency is disabled and 16.7 Hz when zero latency is enabled. The sinc3 filter gives 50 Hz ± 1 Hz rejection of 95 dB minimum for a stable master clock. where: fADC is the output data rate.
Data Sheet AD7194 Simultaneous 50 Hz and 60 Hz rejection is obtained when FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in Figure 41. The output data rate is 10 Hz when zero latency is disabled and 3.3 Hz when zero latency is enabled. The sinc3 filter has rejection of 100 dB minimum at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz. 0 –10 –20 –40 With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped.
AD7194 Data Sheet CH A CH A CH B CH B CH B CH B CH B 1/fADC 4 Figure 44. Channel Change (Sinc Chop Enabled) –30 –40 –50 –60 –70 –80 –90 –100 When conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input; therefore, it continues to output conversions at the programmed output data rate. However, it is at least two conversions later before the output data accurately reflects the analog input.
Data Sheet AD7194 With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded. The analog input pins invert and another settled conversion is obtained. Subsequent conversions are averaged to minimize the offset.
AD7194 Data Sheet The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown in Figure 52 is achieved. The output data rate is unchanged but the 50 Hz/60 Hz ± 1 Hz rejection improves to 73 dB typically. The settling time is equal to tSETTLE = 1/fADC Table 34 lists sample FS words and the corresponding output data rates and settling times. Table 34.
Data Sheet AD7194 fNOTCH = fCLK/(1024 × FS[9:0]) The postfiltering places notches at fNOTCH/Avg (Avg is the amount of averaging) and multiples of this frequency; therefore, when FS[9:0] is set to 6 and the postfilter averaging is 16, a notch is placed at 800 Hz due to the sinc filter and notches are placed at 50 Hz and multiples of 50 Hz due to the postfilter. The notch at 50 Hz is a first-order notch; therefore, the notch is not wide.
AD7194 Data Sheet In fast settling mode, the settling time is close to the inverse of the first filter notch. Therefore, the user can achieve 50 Hz and/or 60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz. The settling time is equal to 1/output data rate. Therefore, the conversion time is constant when converting on a single channel or when converting on several channels. There is no added latency when switching channels.
AD7194 0 –10 –20 –20 –30 –30 –40 –40 –50 –60 –70 –80 –60 –70 –80 –90 –90 –100 –100 –110 –110 –120 –120 30 60 90 120 150 FREQUENCY (Hz) 0 0 –10 0 –30 –10 –40 –20 –50 –30 FILTER GAIN (dB) –60 –70 –80 –90 –100 –50 –60 –70 –80 –100 120 150 08566-063 –90 –120 90 150 –40 –110 60 120 Simultaneous 50 Hz and 60 Hz rejection is also achieved by using an FS word of 96 and averaging by 16, which places a notch at 50 Hz.
AD7194 Data Sheet FAST SETTLING MODE (CHOP ENABLED) Chop can be enabled in the fast settling mode. With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded. The analog input pins are then inverted, and another settled conversion is obtained. Subsequent conversions are averaged so that the offset is minimized.
Data Sheet AD7194 SUMMARY OF FILTER OPTIONS The AD7194 has several filter options. The filter that is chosen affects the output data rate, settling time, the rms noise, the stop band attenuation, and the 50 Hz/60 Hz rejection. Table 36 shows some sample configurations and the corresponding performance in terms of throughput, settling time and 50 Hz/60 Hz rejection. Table 36.
AD7194 Data Sheet GROUNDING AND LAYOUT Because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are commonmode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog and digital supplies to the AD7194 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device.
Data Sheet AD7194 APPLICATIONS INFORMATION In Figure 67, temperature compensation is performed using a thermistor. In addition, the reference voltage for the temperature measurement is derived from a precision resistor in series with the thermistor. This allows a ratiometric measurement so that variation of the excitation voltage has no affect on the measurement (it is the ratio of the precision reference resistance to the thermistor resistance that is measured).
AD7194 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 0.50 BSC 0.80 0.75 0.70 0.50 0.40 0.30 8 16 9 BOTTOM VIEW 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.65 3.50 SQ 3.45 EXPOSED PAD 17 TOP VIEW PIN 1 INDICATOR 1 24 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 04-02-2012-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 68.
Data Sheet AD7194 NOTES Rev.
AD7194 Data Sheet NOTES ©2009–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08566-0-3/13(A) Rev.
