Datasheet

AD7193 Data Sheet
Rev. D | Page 50 of 56
FAST SETTLING MODE (SINC
3
FILTER)
In fast settling mode, the settling time is close to the inverse of
the first filter notch. Therefore, the user can achieve 50 Hz and/or
60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz.
The settling time is equal to 1/output data rate. Therefore, the
conversion time is constant when converting on a single channel
or when converting on several channels. There is no added
latency when switching channels.
The fast settling mode is enabled using Bit AVG1 and Bit AVG0
in the mode register. A postfilter is included after the sinc
4
filter.
The postfilter averages by 2, 8, or 16, depending on the settings
of the AVG1 and AVG0 bits.
SINC
3
/SINC
4
POST FILTERMODULATOR
ADC
CHOP
08367-055
Figure 61. Fast Settling Mode, Sinc
3
Filter
Output Data Rate and Settling Time, Sinc
3
Filter
With chop disabled, the output data rate is
f
ADC
= f
CLK
/((3 + Avg – 1) × 1024 × FS[9:0])
f
ADC
is the output data rate.
f
CLK
is master clock (4.92 MHz nominal).
Avg is the average.
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
If AVG1 = AVG0 = 0, the fast settling mode is not enabled.
In this case, the preceding equation is not relevant.
The settling time is equal to
t
SETTLE
= 1/f
ADC
Table 35 lists some sample FS words and the corresponding
output data rates and settling times.
Table 35. Examples of Output Data Rates and the
Corresponding Settling Time (Fast Settling Mode, Sinc
3
)
FS[9:0] Average Output Data Rate (Hz) Settling Time (ms)
96 16 2.78 360
30 16 8.9 112.5
6 16 44.44 22.5
5 16 53.3 18.75
If the analog input channel is changed, there is no additional
delay in generating valid conversions and the device functions
as a zero latency ADC.
CHANNEL
CONVERSIONS
CHANNEL A
CH A CH A CH A CH BCH B CH B CH B
CHANNEL B
1/
f
ADC
CH BCH B
0
8367-056
Figure 62. Fast Settling, Sinc
3
Filter
When the device is converting on a single channel and a step
change occurs on the analog input, the ADC does not detect
the change and continues to output conversions. When the step
change is synchronized with the conversion, only fully settled
results are output from the ADC. However, if the step change is
asynchronous to the conversion process, one intermediate result
is not completely settled (see Figure 63).
ANALOG
INPUT
ADC
OUTPUT
VALID
1/ f
ADC
0
8367-057
Figure 63. Step Change on Analog Input, Sinc
3
Filter
50 Hz/60 Hz Rejection, Sinc
3
Filter
Figure 64 shows the frequency response when FS[9:0] is set to 6
and the postfilter averages by 16. This gives an output data rate
of 44.44 Hz when the master clock is 4.92 MHz. The sinc filter
places the first notch at
f
NOTCH
= f
CLK
/(1024 × FS[9:0])
The postfiltering places notches at f
NOTCH
/Avg (Avg is the amount
of averaging) and multiples of this frequency. Therefore, when
FS[9:0] is set to 6 and the postfilter averaging is 16, a notch is
placed at 800 Hz due to the sinc filter and notches are placed at
50 Hz and multiples of 50 Hz due to the postfilter.
The notch at 50 Hz is a first-order notch. Therefore, the notch is
not wide. This means that the rejection at 50 Hz exactly is good,
assuming a stable 4.92 MHz master clock. However, in a band of
50 Hz ± 1 Hz, the rejection degrades significantly. The rejection at
50 Hz ± 0.5 Hz is 40 dB minimum, assuming a stable clock; there-
fore, a good master clock source is recommended when using fast
settling mode.
08367-053
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 306090120150
FREQUENCY (Hz)
FILTER GAIN (dB)
Figure 64. Filter Response for Average + Decimate Filter
(Sinc
3
Filter, FS[9:0] = 6, Average by 16)