Datasheet

AD7193 Data Sheet
Rev. D | Page 44 of 56
Sinc
3
Zero Latency
Zero latency is enabled by setting the single bit (Bit 11) in the
mode register to 1. With zero latency, the complete settling time
is allowed for each conversion. Therefore, the conversion time
when converting on a single channel or when converting on
several channels is constant. The user does not need to consider
the effects of channel changes on the output data rate. When the
channel sequencer is enabled, the AD7193 automatically operates
in zero latency mode.
The output data rate equals
f
ADC
= 1/ t
SETTLE
= f
CLK
/(3 × 1024 × FS[9:0])
where:
f
ADC
is the output data rate.
f
CLK
is the master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
When the analog input is constant or a channel change occurs,
valid conversions are available at a constant output data rate.
When conversions are being performed on a single channel and
a step change occurs on the analog input, the ADC continues to
output fully settled conversions if the step change is synchronized
with the conversion process. If the step change is asynchronous,
one conversion is output from the ADC that is not completely
settled (see Figure 39).
ANALOG
INPUT
ADC
OUTPUT
FULLY
SETTLED
1/
f
ADC
08367-035
Figure 39. Sinc
3
Zero Latency Operation
Table 31 provides examples of output data rates and the
corresponding FS values.
Table 31. Examples of Output Data Rates and the
Corresponding Settling Time (Zero Latency)
FS[9:0] Output Data Rate (Hz) Settling Time (ms)
480 3.3 300
96 16.7 60
80 20 50
Sinc
3
50 Hz/60 Hz Rejection
Figure 40 show the frequency response of the sinc
3
filter when
FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The
output data rate is equal to 50 Hz when zero latency is disabled
and 16.7 Hz when zero latency is enabled. The sinc
3
filter gives
50 Hz ± 1 Hz rejection of 95 dB minimum for a stable master clock.
–120
–1
10
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 25 50
75
100
125
150
FREQUENC
Y (Hz)
FILTER GAIN (dB)
08367-036
Figure 40. Sinc
3
Filter Response (FS[9:0] = 96)
When FS[9:0] is set to 80 and the master clock equals 4.92 MHz,
60 Hz rejection is achieved (see Figure 41). The output data rate
is equal to 60 Hz when zero latency is disabled and 20 Hz when
zero latency is enabled. The sinc
3
filter has rejection of 95 dB
minimum at 60 Hz ± 1 Hz, assuming a stable master clock.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0
30
60
90
120
150
FREQUENCY (Hz)
FILTER GAIN (dB)
08367-037
Figure 41. Sinc
3
Filter Response (FS[9:0] = 80)