Datasheet
Data Sheet AD7193
Rev. D | Page 43 of 56
Simultaneous 50 Hz/60 Hz rejection can also be achieved using
the REJ60 bit in the mode register. When FS[9:0] is set to 96
and REJ60 is set to 1, notches are placed at 50 Hz and 60 Hz.
The output data rate is 50 Hz when zero latency is disabled and
12.5 Hz when zero latency is enabled. Figure 35 shows the
frequency response of the sinc
4
filter. The filter provides 50 Hz
± 1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum,
assuming a stable 4.92 MHz master clock.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 25 50 75 100 125 150
FREQUENCY (Hz)
FILTER GAIN (dB)
08367-031
Figure 35. Sinc
4
Filter Response (FS[9:0] = 96, REJ60 = 1)
SINC
3
FILTER (CHOP DISABLED)
A sinc
3
filter can be used instead of the sinc
4
filter. The filter is
selected using the SINC3 bit in the mode register. The sinc
3
filter is selected when the SINC3 bit is set to 1.
This filter has good noise performance when operating with
output data rates up to 1 kHz. It has moderate settling time and
moderate 50 Hz/60 Hz (±1 Hz) rejection.
SINC
3
/SINC
4
POST FILTERMODULATOR
ADC
CHOP
08367-032
Figure 36. Sinc
3
Filter (Chop Disabled)
Sinc
3
Output Data Rate and Settling Time
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
f
ADC
= f
CLK
/(1024 × FS[9:0])
where:
f
ADC
is the output data rate.
f
CLK
is the master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to
4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.
The settling time is equal to
t
SETTLE
= 3/f
ADC
The 3 dB frequency is equal to
f
3dB
= 0.272 × f
ADC
Table 30 gives some examples of FS settings and the corresponding
output data rates and settling times.
Table 30. Examples of Output Data Rates and the
Corresponding Settling Time
FS[9:0] Output Data Rate (Hz) Settling Time (ms)
480 10 300
96 50 60
80 60 50
When a channel change occurs, the modulator and filter reset. The
complete settling time is allowed to generate the first conversion
after the channel change (see Figure 37). Subsequent conversions
on this channel are available at 1/f
ADC
.
CHANNEL
CONVERSIONS
CHANNEL A
CH A CH A CH A CH BCH B CH B CH B
CHANNEL B
1/
f
ADC
0
8367-033
Figure 37. Sinc
3
Channel Change
When conversions are performed on a single channel and a
step change occurs, the ADC does not detect the change in
analog input. Therefore, it continues to output conversions at
the programmed output data rate. However, it is at least three
conversions later before the output data accurately reflects the
analog input. If the step change occurs while the ADC is processing
a conversion, the ADC takes four conversions after the step change
to generate a fully settled result.
1/
f
ADC
ANALOG
INPUT
ADC
OUTPUT
FULLY
SETTLED
08367-034
Figure 38. Asynchronous Step Change in Analog Input