Datasheet
Data Sheet AD7193
Rev. D | Page 41 of 56
DIGITAL FILTER
The AD7193 offers a lot of flexibility in the digital filter. The
device has five filter options. The device can be operated with
a sinc
3
or sinc
4
filter, chop can be enabled or disabled, and zero
latency can be enabled. Finally, an averaging block can be
included after the sinc filter, which gives a fast settling mode.
The option selected affects the output data rate, settling time,
and 50 Hz/60 Hz rejection. The following sections describe
each filter type, indicating the available output data rates for
each filter option. The filter response, along with the settling
time and 50 Hz/60 Hz rejection, is also discussed.
SINC
4
FILTER (CHOP DISABLED)
When the AD7193 is powered up, the sinc
4
filter is selected by
default and chop is disabled. This filter gives excellent noise
performance over the complete range of output data rates. It
also gives the best 50 Hz/60 Hz rejection, but it has a long
settling time.
SINC
3
/SINC
4
POST FILTERMODULATOR
ADC
CHOP
08367-024
Figure 28. Sinc
4
Filter (Chop Disabled)
Sinc
4
Output Data Rate/Settling Time
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
f
ADC
= f
CLK
/(1024 × FS[9:0])
where:
f
ADC
is the output data rate.
f
CLK
is the master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to
4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.
The settling time for the sinc
4
filter is equal to
t
SETTLE
= 4/f
ADC
When a channel change occurs, the modulator and filter are
reset. The settling time is allowed to generate the first conver-
sion after the channel change. Subsequent conversions on this
channel occur at 1/f
ADC
.
CHANNEL
CONVERSIONS
CHANNEL A
CH A CH A CH A CH B CH B CH B
CHANNEL B
1/
f
ADC
0
8367-025
Figure 29. Sinc
4
Channel Change
When conversions are performed on a single channel and a step
change occurs, the ADC does not detect the change in analog
input. Therefore, it continues to output conversions at the pro-
grammed output data rate. However, it is at least four conversions
later before the output data accurately reflect the analog input.
If the step change occurs while the ADC is processing a conver-
sion, then the ADC takes five conversions after the step change
to generate a fully settled result.
1/
f
ADC
ANALOG
INPUT
ADC
OUTPUT
FULLY
SETTLED
08367-026
Figure 30. Asynchronous Step Change in Analog Input
The 3 dB frequency for the sinc
4
filter is equal to
f
3dB
= 0.23 × f
ADC
Table 28 gives some examples of the relationship between the
values in Bits FS[9:0] and the corresponding output data rate
and settling time.
Table 28. Examples of Output Data Rates and the
Corresponding Settling Time
FS[9:0] Output Data Rate (Hz) Settling Time (ms)
480 10 400
96 50 80
80 60 66.6
Sinc
4
Zero Latency
Zero latency is enabled by setting the single bit (Bit 11) in the
mode register to 1. With zero latency, the complete settling time
is allowed for each conversion. Therefore, the conversion time
when converting on a single channel or when converting on
several channels is constant. The user does not need to consider
the effects of channel changes on the output data rate. When the
channel sequencer is enabled, the AD7193 automatically
operates in zero latency mode.
The output data rate equals
f
ADC
= 1/t
SETTLE
= f
CLK
/(4 × 1024 × FS[9:0])
where:
f
ADC
is the output data rate.
f
CLK
is the master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.