Datasheet

Data Sheet AD7193
Rev. D | Page 35 of 56
The AD7193 can be operated with
CS
used as a frame synchro-
nization signal. This scheme is useful for DSP interfaces. In this
case, the first bit (MSB) is effectively clocked out by
CS
because
CS
normally occurs after the falling edge of SCLK in DSPs. The
SCLK can continue to run between data transfers, provided the
timing numbers are obeyed.
The serial interface can be reset by writing a series of 1s to the
DIN input. If a Logic 1 is written to the AD7193 DIN line for
at least 40 serial clock cycles, the serial interface is reset. This
ensures that the interface can be reset to a known state if the
interface is lost due to a software error or a glitch in the system.
Reset returns the interface to the state in which it expects a write to
the communications register. This operation resets the contents
of all registers to their power-on values. Following a reset, the
user should allow a period of 500 µs before addressing the serial
interface.
The AD7193 can be configured to continuously convert or to
perform a single conversion (see Figure 25 through Figure 27).
Single Conversion Mode
In single conversion mode, the AD7193 is placed in power-
down mode after conversions. When a single conversion is
initiated by setting MD2 to 0, MD1 to 0, and MD0 to 1 in
the mode register, the AD7193 powers up, performs a single
conversion, and then returns to power-down mode. The on-
chip oscillator requires 1 ms, approximately, to power up.
DOUT/
RDY
goes low to indicate the completion of a conversion.
When the data-word has been read from the data register,
DOUT/
RDY
goes high. If
CS
is low, DOUT/
RDY
remains high
until another conversion is initiated and completed. The data
register can be read several times, if required, even when
DOUT/
RDY
has gone high.
If several channels are enabled, the ADC sequences through the
enabled channels and performs a conversion on each channel.
When a conversion is started, DOUT/
RDY
goes high and remains
high until a valid conversion is available. As soon as the conversion
is available, DOUT/
RDY
goes low. The ADC then selects the
next channel and begins a conversion. The user can read the
present conversion while the next conversion is being performed.
As soon as the next conversion is complete, the data register is
updated; therefore, the user has a limited period in which to
read the conversion. When the ADC has performed a single
conversion on each of the selected channels, it returns to power-
down mode.
If the DAT_STA bit in the mode register is set to 1, the contents
of the status register are output along with the conversion each
time that the data read is performed. The four LSBs of the status
register indicate the channel to which the conversion corresponds.
DIN
SCLK
DOUT/RDY
CS
0x08 0x58
DATA
0x280060
08367-061
Figure 25. Single Conversion