Datasheet
AD7193 Data Sheet
Rev. D | Page 24 of 56
MODE REGISTER
RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060
The mode register is a 24-bit register from which data can be
read or to which data can be written. This register is used to
select the operating mode, the output data rate, and the clock
source. Table 20 outlines the bit designations for the mode
register. MR0 through MR23 indicate the bit locations, MR
denoting that the bits are in the mode register. MR23 denotes
the first bit of the data stream. The number in parentheses
indicates the power-on/reset default status of that bit. Any write
to the mode register resets the modulator and filter and sets the
RDY
bit.
MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16
MD2(0) MD1(0) MD0(0) DAT_STA(0) CLK1(1) CLK0(0) AVG1(0) AVG0(0)
MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8
SINC3(0) 0 ENPAR(0) CLK_DIV(0) Single(0) REJ60(0) FS9(0) FS8(0)
MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
FS7(0) FS6(1) FS5(1) FS4(0) FS3(0) FS2(0) FS1(0) FS0(0)
Table 20. Mode Register (MR) Bit Designations
Bit Location Bit Name Description
MR23 to MR21 MD2 to MD0 Mode select bits. These bits select the operating mode of the AD7193 (see Table 21).
MR20 DAT_STA This bit enables the transmission of status register contents after each data register read. When DAT_STA
is set, the contents of the status register are transmitted along with each data register read. This function
is useful when several channels are selected because the status register identifies the channel to which
the data register value corresponds.
MR19, MR18 CLK1, CLK0 These bits select the clock source for the AD7193. Either the on-chip 4.92 MHz clock or an external clock
can be used. The ability to use an external clock allows several AD7193 devices to be synchronized. Also,
50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7193.
CLK1
CLK0
ADC Clock Source
0 0 External crystal. The external crystal is connected from MCLK1 to MCLK2.
0 1 External clock. The external clock is applied to the MCLK2 pin.
1 0 Internal 4.92 MHz clock. Pin MCLK2 is tristated.
1
1
Internal 4.92 MHz clock. The internal clock is available on MCLK2.
MR17, MR16 AVG1, AVG0 Fast settling filter. When this option is selected, the settling time equals one conversion time. In fast
settling mode, a first-order average and decimate block is included after the sinc filter. The data from the
sinc filter is averaged by 2, 8, or 16. The averaging reduces the output data rate for a given FS word;
however, the rms noise improves. The AVG1 and AVG0 bits select the amount of averaging. Fast settling
mode can be used for FS words less than 512 only. When the sinc
3
filter is selected, the FS word must be
less than 256 when averaging by 16.
AVG1 AVG0 Average
0 0 No averaging (fast settling mode disabled)
0 1 Average by 2
1 0 Average by 8
1 1 Average by 16
MR15 SINC3 Sinc
3
filter select bit. When this bit is cleared, the sinc
4
filter is used (default value). When this bit is set,
the sinc
3
filter is used. The benefit of the sinc
3
filter compared to the sinc
4
filter is its lower settling time.
For a given output data rate, f
ADC
, the sinc
3
filter has a settling time of 3/f
ADC
whereas the sinc
4
filter has
a settling time of 4/f
ADC
when chop is disabled. The sinc
4
filter, due to its deeper notches, gives better
50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no missing
codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc
4
filter gives
better performance than the sinc
3
filter for rms noise and no missing codes.
MR14 0 This bit must be programmed with a Logic 0 for correct operation.
MR13 ENPAR Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit in
the mode register
should be set when the parity check is used. When the DAT_STA bit is set, the contents
of the status register are transmitted along with the data for each data register read.