Datasheet

Data Sheet AD7193
Rev. D | Page 21 of 56
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers that are described on the following pages wherein the term set
implies a Logic 1 state and the term cleared implies a Logic 0 state, unless otherwise noted.
Table 16. Register Summary
Register Addr. Dir. Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Communications 00 W 00
WEN
R/
W
Register address
CREAD 0 0
Status 00 R 80
RDY
ERR NOREF Parity CHD3 CHD2 CHD1 CHD0
Mode 01 R/W 080060 Mode select DAT_STA CLK1 CLK0 AVG1 AVG0
SINC3 0 ENPAR CLK_DIV Single REJ60 FS9 FS8
FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 (LSB)
Configuration 02 R/W 000117 Chop (MSB) 0 0 REFSEL 0 Pseudo Short TEMP
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
Burn REFDET 0 BUF U/
B
G2 G1 G0 (LSB)
Data 03 R 000000 D23 (MSB) D22 D21 D20 D19 D18 D17 D16
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0 (LSB)
ID 04 R X2 X X X X 0 0 1 0
GPOCON 05 R/W 00 0 BPDSW GP32EN GP10EN P3DAT P2DAT P1DAT P0DAT
Offset 06 R/W 800000 OF23 (MSB) OF22 OF21 OF20 OF19 OF18 OF17 OF16
OF15 OF14 OF13 OF12 OF11 OF10 OF9 OF8
OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 (LSB)
Full Scale 07 R/W 5XXXX0 FS23 (MSB) FS22 FS21 FS20 FS19 FS18 FS17 FS16
FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8
FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 (LSB)