4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA AD7193 Data Sheet FEATURES Pressure measurement Temperature measurement Flow measurement Weigh scales Chromatography Medical and scientific instrumentation Fast settling filter option 4 differential/8 pseudo differential input channels RMS noise: 11 nV @ 4.7 Hz (gain = 128) 15.5 noise-free bits @ 2.
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AD7193 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Reference ..................................................................................... 32 Applications ....................................................................................... 1 Reference Detect ......................................................................... 33 General Description ................................................
Data Sheet AD7193 REVISION HISTORY Added 32-Lead LFCSP ...................................................... Universal Changes to Table 7 ..........................................................................17 Changes to Communications Register, Table 16 .........................20 Updated Outline Dimensions ........................................................54 Changes to Ordering Guide ...........................................................
AD7193 Data Sheet SPECIFICATIONS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = 2.5 V or AVDD, REFINx(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter ADC Output Data Rate No Missing Codes 2 Min Typ 4.7 1.17 1.56 24 24 Resolution RMS Noise and Output Data Rates Integral Nonlinearity Gain = 12 ±2 ±2 ±5 ±15 ±150/gain ±1 ±0.5 ±150/gain Gain > 1 Offset Error 4, 5 Offset Error Drift vs.
Data Sheet Parameter Normal-Mode Rejection2 Sinc4 Filter Internal Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz Sinc3 Filter Internal Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 50 Hz @ 60 Hz Fast Settling Internal Clock @ 50 Hz AD7193 Unit Test Conditions/Comments 1 100 dB 74 dB 96 97 dB dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 50 Hz output data rate, REJ60 6 = 1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 50 Hz output data rate
AD7193 Parameter REFERENCE INPUT REFIN Voltage Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift Data Sheet Max Unit Test Conditions/Comments 1 1 AVDD V REFIN = REFINx(+) − REFINx(−), the differential input must be limited to ±(AVDD − 1.25 V)/gain when gain > 1 AGND − 0.05 AVDD + 0.
Data Sheet Parameter Data Output Coding SYSTEM CALIBRATION2 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS 7 Power Supply Voltage AVDD − AGND DVDD − DGND Power Supply Currents AIDD Current DIDD Current IDD AD7193 Min Typ Offset binary Max Unit 1.05 × FS V V 0.8 × FS 2.1 × FS V 3 2.7 5.25 5.25 V V 1 1.25 3.6 3.9 4.7 5.3 0.4 0.6 mA mA mA mA mA mA mA mA mA µA −1.05 × FS 0.85 1 2.8 3.2 3.8 4.3 0.35 0.5 1.
AD7193 Data Sheet TIMING CHARACTERISTICS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2.
Data Sheet AD7193 CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 08367-003 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev.
AD7193 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. Parameter AVDD to AGND DVDD to AGND AGND to DGND Analog Input Voltage to AGND Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND AINx/Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Temperature, Soldering Reflow Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +0.3 V −0.3 V to AVDD + 0.3 V −0.
Data Sheet AD7193 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS MCLK1 1 28 DIN MCLK2 2 27 DOUT/RDY SCLK 3 26 SYNC CS 4 25 DVDD P3 5 24 AVDD P0/REFIN2(–) 8 NC 9 AINCOM 10 AIN1 11 AD7193 TOP VIEW (Not to Scale) 23 DGND 22 AGND 21 BPDSW 20 REFIN1(–) 19 REFIN1(+) 18 AIN8 AIN2 12 17 AIN7 AIN3 13 16 AIN6 AIN4 14 15 AIN5 NC = NO CONNECT 08367-005 P2 6 P1/REFIN2(+) 7 Figure 5. 28-lead TSSOP Pin Configuration Table 5. 28-lead TSSOP Pin Function Descriptions Pin No.
AD7193 Data Sheet Pin No. 14 Mnemonic AIN4 15 AIN5 16 AIN6 17 AIN7 18 AIN8 19 REFIN1(+) 20 21 22 23 24 REFIN1(−) BPDSW AGND DGND AVDD 25 DVDD 26 SYNC 27 DOUT/RDY 28 DIN Description Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudo differential input when used with AINCOM. Analog Input.
AD7193 32 31 30 29 28 27 26 25 CS SCLK MCLK2 MCLK1 DIN DOUT/RDY NC SYNC Data Sheet 1 2 3 4 5 6 7 8 AD7193 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 DVDD AVDD DGND AGND BPDSW NC REFIN1(–) REFIN1(+) NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO AGND. 08367-065 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 9 10 11 12 13 14 15 16 P3 P2 P1/REFIN2(+) P0/REFIN2(–) NC NC NC AINCOM Figure 6. 32-Lead LFCSP Pin Configuration Table 6. 32-Lead LFCSP Pin Function Descriptions Pin No.
AD7193 Data Sheet Pin No. 21 22 23 Mnemonic AGND DGND AVDD 24 DVDD 25 SYNC 27 DOUT/RDY 28 DIN 29 MCLK1 30 MCLK2 31 SCLK 32 CS EPAD Description Analog Ground Reference Point. Digital Ground Reference Point. Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with AVDD at 5 V or vice versa. Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V with DVDD at 5 V or vice versa.
Data Sheet AD7193 TYPICAL PERFORMANCE CHARACTERISTICS 8,387,486 50 8,387,484 40 8,387,482 OCCURRENCE CODE 8,387,480 8,387,478 8,387,476 8,387,474 30 20 8,387,472 10 0 200 400 600 800 1000 SAMPLE 0 8,388,830 08367-006 8,387,468 8,388,890 8,388,860 08367-009 8,387,470 8,388,920 CODE Figure 10. Noise Distribution Histogram (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc4 Filter) Figure 7. Noise (VREF = AVDD = 5 V, Output Data Rate = 4.
AD7193 Data Sheet 0.4 5 0.2 4 0 –0.2 OFFSET (µV) INL (ppm of FSR) 3 2 1 –0.4 –0.6 –0.8 0 –1.0 –1 –2 –1 0 2 1 4 3 VIN (V) –1.4 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 08367-015 –3 08367-012 –2 –4 –1.2 Figure 16. Offset vs. Temperature (Gain = 128, Chop Disabled) Figure 13. INL (Gain = 1) 1.000008 20 1.000006 15 1.000004 10 1.000000 GAIN INL (ppm of FSR) 1.000002 5 0 0.999998 0.999996 –5 0.999994 –10 0.999992 –15 0 0.01 0.02 0.03 VIN (V) 0.
Data Sheet AD7193 23 GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128 22 GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128 22 NOISE FREE RESOLUTION (Bits) NOISE FREE RESOLUTION (Bits) 24 20 18 16 21 20 19 18 1 10 100 1k 10k OUTPUT DATA RATE (Hz) Figure 19.
AD7193 Data Sheet RMS NOISE AND RESOLUTION is continuously converting on a single channel. It is important to note that the effective resolution is calculated using the rms noise, whereas the peak-to-peak resolution is calculated based on peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker. With chop enabled, the resolution improves by 0.5 bits.
Data Sheet AD7193 SINC3 CHOP DISABLED Table 10. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 20 10 3.13 1.25 0.
AD7193 Data Sheet FAST SETTLING Table 13. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 96 30 6 5 2 1 Average 16 16 16 16 16 16 Output Data Rate (Hz) 2.63 8.4 42.10 50.53 126.32 252.63 Settling Time (ms) 380 118.75 23.75 19.79 7.92 3.96 1 380 620 1300 1500 2300 3400 8 87 140 270 280 380 520 16 52 71 150 160 210 290 Gain of 32 33 43 82 88 130 180 64 15 30 56 61 88 130 128 11 21 47 50 77 110 64 100 190 360 390 580 820 128 70 130 300 330 510 740 64 23.2 (20.6) 22.3 (19.6) 21.
Data Sheet AD7193 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described on the following pages wherein the term set implies a Logic 1 state and the term cleared implies a Logic 0 state, unless otherwise noted. Table 16. Register Summary Register Communications Addr. 00 Dir.
AD7193 Data Sheet COMMUNICATIONS REGISTER RS2, RS1, RS0 = 000 The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determine whether the next operation is a read or write operation and in which register this operation occurs.
Data Sheet AD7193 STATUS REGISTER RS2, RS1, RS0 = 000; Power-On/Reset = 0x80 The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read operation, and SR7 RDY(1) SR6 ERR(0) SR5 NOREF(0) SR4 Parity(0) load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 19 outlines the bit designations for the status register.
AD7193 Data Sheet MODE REGISTER RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060 The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the output data rate, and the clock source. Table 20 outlines the bit designations for the mode MR23 MD2(0) MR15 SINC3(0) MR7 FS7(0) MR22 MD1(0) MR14 0 MR6 FS6(1) MR21 MD0(0) MR13 ENPAR(0) MR5 FS5(1) MR20 DAT_STA(0) MR12 CLK_DIV(0) MR4 FS4(0) register.
Data Sheet AD7193 Bit Location MR12 Bit Name CLK_DIV MR11 Single MR10 REJ60 MR9 to MR0 FS9 to FS0 Description Clock divide-by-2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, set this bit to 0. When performing internal full-scale calibrations, this bit must be set when AVDD is less than 4.75 V. The calibration accuracy is optimized when chop is enabled and a low output data rate is used while performing the calibration. When AVDD is greater than or equal to 4.
AD7193 Data Sheet MD2 1 MD1 0 MD0 0 1 0 1 1 1 0 1 1 1 Mode Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. Internal full-scale calibration.
Data Sheet AD7193 CONFIGURATION REGISTER RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117 The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel.
AD7193 Data Sheet Bit Location CON4 Bit Name BUF CON3 U/B CON2 to CON0 G2 to G0 Description Enables the buffer on the analog inputs. If BUF is set, the analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain errors to the system. When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin must be limited to 250 mV within the power supply rails.
Data Sheet AD7193 DATA REGISTER GPOCON REGISTER RS2, RS1, RS0 = 011; Power-On/Reset = 0x000000 RS2, RS1, RS0 = 101; Power-On/Reset = 0x00 The conversion result from the ADC is stored in this data register. This is a read-only, 24-bit register. Upon completion of a read operation from this register, the RDY pin/bit is set. When the DAT_STA bit in the mode register is set to 1, the contents of the status register are appended to each 24-bit conversion.
AD7193 Data Sheet OFFSET REGISTER FULL-SCALE REGISTER RS2, RS1, RS0 = 110; Power-On/Reset = 0x800000) RS2, RS1, RS0 = 111; Power-On/Reset = 0x5XXXX0 The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The AD7193 has five offset registers. In differential mode, each channel has a dedicated offset register.
Data Sheet AD7193 ADC CIRCUIT INFORMATION 5V REFIN1(+) AGND OUT+ OUT– IN– AIN1 AIN2 AIN3 AIN4 AIN5 MUX AIN6 AIN7 AIN8 AINCOM AVDD DVDD DGND REFERENCE DETECT AVDD MODULATOR AND FILTER PGA Σ-Δ ADC SERIAL INTERFACE AND CONTROL LOGIC CALIBRATION AGND TEMP SENSOR REFIN1(–) DOUT/RDY DIN SCLK CS SYNC P3 P2 BPDSW AD7193 CLOCK CIRCUITRY AGND MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+) 08367-023 IN+ Figure 22.
AD7193 Data Sheet The AD7193 has four differential/eight pseudo differential analog input channels that can be buffered or unbuffered. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. Therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive type sensors such as strain gages or resistance temperature detectors (RTDs).
Data Sheet AD7193 REFERENCE DETECT The AD7193 includes on-chip circuitry to detect whether the part has a valid reference for conversions or calibrations. This feature is enabled when the REFDET bit in the configuration register is set to 1. If the voltage between the selected REFINx(+) and REFINx(−) pins is less than 0.3 V, the AD7193 detects that it no longer has a valid reference. In this case, the NOREF bit of the status register is set to 1.
AD7193 Data Sheet DIGITAL INTERFACE In continuous conversion mode, the ADC selects each of the enabled channels in sequence and performs a conversion on the channel. The DOUT/RDY pin indicates when a valid conversion is available on each channel. When several channels are enabled, the contents of the status register should be attached to the 24-bit word allowing the user to identify the channel that corresponds to each conversion.
Data Sheet AD7193 The AD7193 can be operated with CS used as a frame synchronization signal. This scheme is useful for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS because CS normally occurs after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers, provided the timing numbers are obeyed. DOUT/RDY goes low to indicate the completion of a conversion. When the data-word has been read from the data register, DOUT/RDY goes high.
AD7193 Data Sheet Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7193 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is completed. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, DOUT/RDY goes high.
Data Sheet AD7193 Continuous Read To exit the continuous read mode, Instruction 01011000 must be written to the communications register while the RDY pin is low. While in the continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit the continuous read mode. Additionally, a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device.
AD7193 Data Sheet RESET ENABLE PARITY The circuitry and serial interface of the AD7193 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, whereas all on-chip registers are reset to their default values. A reset is automatically performed on power-up. When a reset is initiated, the user must allow a period of 500 µs before accessing any of the on-chip registers.
Data Sheet AD7193 TEMPERATURE SENSOR Embedded in the AD7193 is a temperature sensor. This is selected using the TEMP bit in the configuration register. When the TEMP bit is set to 1, the temperature sensor is enabled. When the temperature sensor is selected and bipolar mode is selected, the device should return a code of 0x800000 when the temperature is 0 Kelvin, theoretically. A one-point calibration is needed to obtain the optimum performance from the sensor.
AD7193 Data Sheet The offset error is, typically, ±150 µV/gain. If the gain is changed, it is advisable to perform a calibration. A zero-scale calibration (an internal zero-scale calibration or a system zero-scale calibration) reduces the offset error to the order of the noise. The gain error of the AD7193 is factory calibrated at a gain of 1 with a 5 V power supply at ambient temperature. Following this calibration, the gain error is, typically, ±0.001% at 5 V.
Data Sheet AD7193 DIGITAL FILTER The AD7193 offers a lot of flexibility in the digital filter. The device has five filter options. The device can be operated with a sinc3 or sinc4 filter, chop can be enabled or disabled, and zero latency can be enabled. Finally, an averaging block can be included after the sinc filter, which gives a fast settling mode. The option selected affects the output data rate, settling time, and 50 Hz/60 Hz rejection.
AD7193 Data Sheet When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. When conversions are being performed on a single channel and a step change occurs on the analog input, the ADC continues to output fully settled conversions if the step change is synchronized with the conversion process. If the step change is asynchronous, one conversion is output from the ADC, which is not completely settled (see Figure 31).
Data Sheet AD7193 Simultaneous 50 Hz/60 Hz rejection can also be achieved using the REJ60 bit in the mode register. When FS[9:0] is set to 96 and REJ60 is set to 1, notches are placed at 50 Hz and 60 Hz. The output data rate is 50 Hz when zero latency is disabled and 12.5 Hz when zero latency is enabled. Figure 35 shows the frequency response of the sinc4 filter. The filter provides 50 Hz ± 1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, assuming a stable 4.92 MHz master clock.
AD7193 Data Sheet Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection Zero latency is enabled by setting the single bit (Bit 11) in the mode register to 1. With zero latency, the complete settling time is allowed for each conversion. Therefore, the conversion time when converting on a single channel or when converting on several channels is constant. The user does not need to consider the effects of channel changes on the output data rate.
Data Sheet AD7193 Simultaneous 50 Hz and 60 Hz rejection is obtained when FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in Figure 42. The output data rate is 10 Hz when zero latency is disabled and 3.3 Hz when zero latency is enabled. The sinc3 filter has rejection of 100 dB minimum at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz. 0 –10 –20 –40 With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped.
AD7193 Data Sheet CH A CH A CH B CH B CH B CH B CH B 1/fADC –30 –40 –50 –60 –70 –80 –90 Figure 45. Channel Change (Sinc4 Chop Enabled) –100 When conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input; therefore, it continues to output conversions at the programmed output data rate. However, it is at least two conversions later before the output data accurately reflects the analog input.
Data Sheet AD7193 With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded. The analog input pins invert and another settled conversion is obtained. Subsequent conversions are averaged to minimize the offset.
AD7193 Data Sheet The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown in Figure 53 is achieved. The output data rate is unchanged but the 50 Hz/60 Hz ± 1 Hz rejection improves to 73 dB typically. 0 tSETTLE = 1/fADC Table 34 lists sample FS words and the corresponding output data rates and settling times. Table 34.
Data Sheet AD7193 50 Hz/60 Hz Rejection, Sinc4 Filter Figure 57 shows the frequency response when FS[9:0] is set to 6 and the postfilter averages by 16. This gives an output data rate of 42.10 Hz when the master clock equals 4.92 MHz. The sinc filter places the first notch at Simultaneous 50 Hz/60 Hz rejection is achieved when FS[9:0] is set to 30 and the postfilter averages by 16. The output data rate is equal to 8.4 Hz, whereas the rejection at 50 Hz ± 0.5 Hz and 60 Hz ± 0.5 Hz is typically 44 dB.
AD7193 Data Sheet In fast settling mode, the settling time is close to the inverse of the first filter notch. Therefore, the user can achieve 50 Hz and/or 60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz. The settling time is equal to 1/output data rate. Therefore, the conversion time is constant when converting on a single channel or when converting on several channels. There is no added latency when switching channels.
Data Sheet AD7193 0 –20 0 –30 –10 –40 –20 –50 –30 –60 FILTER GAIN (dB) FILTER GAIN (dB) –10 Simultaneous 50 Hz and 60 Hz rejection is also achieved by using an FS word of 96 and averaging by 16, which places a notch at 50 Hz. Setting the REJ60 bit to 1 places a notch at 60 Hz (see Figure 67). The output data rate is reduced to 2.78 Hz with this configuration, but the rejection is improved to 94 dB typically at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz.
AD7193 Data Sheet SUMMARY OF FILTER OPTIONS The AD7193 has several filter options. The filter that is chosen affects the output data rate, settling time, the rms noise, and the 50 Hz/60 Hz rejection. Table 36 shows some sample configurations and the corresponding performance in terms of throughput, settling time, and 50 Hz/ 60 Hz rejection. Table 36.
Data Sheet AD7193 GROUNDING AND LAYOUT Because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are common-mode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog and digital supplies to the AD7193 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device.
AD7193 Data Sheet APPLICATIONS INFORMATION power consumed in the application. In addition, the bridge power-down switch can be opened while the AD7193 is in powerdown mode, thus avoiding unnecessary power consumption by the front-end transducers. When the parts are taken out of power-down mode and the bridge power-down switch is closed, the user should ensure that the front-end circuitry is fully settled before attempting a read from the AD7193.
Data Sheet AD7193 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX SEATING PLANE 8° 0° 0.20 0.09 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 69. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 0.30 0.25 0.18 32 25 0.50 BSC 0.80 0.75 0.70 0.50 0.40 0.30 8 16 9 BOTTOM VIEW 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.
AD7193 Data Sheet NOTES ©2009–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08367-0-3/13(D) Rev.
