Datasheet

AD7192
Rev. A | Page 6 of 40
Parameter AD7192B Unit Test Conditions/Comments
1
SYSTEM CALIBRATION
2
Full-Scale Calibration Limit 1.05 × FS V max
Zero-Scale Calibration Limit −1.05 × FS V min
Input Span 0.8 × FS V min
2.1 × FS V max
POWER REQUIREMENTS
7
Power Supply Voltage
AV
DD
− AGND 3/5.25 V min/max
DV
DD
− DGND 2.7/5.25 V min/max
Power Supply Currents
AI
DD
Current 0.6 mA max 0.53 mA typical, gain = 1, buffer off.
0.85 mA max 0.75 mA typical, gain = 1, buffer on.
3.2 mA max 2.5 mA typical, gain = 8, buffer off.
3.6 mA max 3 mA typical, gain = 8, buffer on.
4.5 mA max 3.5 mA typical, gain = 16 to 128, buffer off.
5 mA max 4 mA typical, gain = 16 to 128, buffer on.
DI
DD
Current 0.4 mA max 0.35 mA typical, DV
DD
= 3 V.
0.6 mA max 0.5 mA typical, DV
DD
= 5 V.
1.5 mA typ External crystal used.
I
DD
(Power-Down Mode) 3 µA max
1
Temperature range: −40°C to +105°C.
2
Specification is not production tested but is supported by characterization data at initial product release.
3
FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.
4
Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-
scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
5
The analog inputs are configured for differential mode.
6
REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.
7
Digital inputs equal to DV
DD
or DGND.