Datasheet

AD7192
Rev. A | Page 25 of 40
ADC CIRCUIT INFORMATION
MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)
DV
DD
DGND
5
V
AIN1
IN+
IN–
OUT–
OUT+
AIN2
AIN3
AIN4
AINCOM
REFIN1(–)
BPDSW
AGND
AD7192
REFIN1(+)
REFERENCE
DETECT
SERIAL
INTERFACE
AND
CONTROL
LOGIC
TEMP
SENSOR
CLOCK
CIRCUITRY
AV
DD
AGND
DOUT/RDY
DIN
SCLK
CS
SYNC
P3
P2
AV
DD
AGND
Σ-Δ
ADC
PGA
MUX
0
7822-012
Figure 18. Basic Connection Diagram
OVERVIEW
The AD7192 is an ultralow noise ADC that incorporates a Σ-Δ
modulator, a buffer, PGA, and on-chip digital filtering intended
for the measurement of wide dynamic range signals such as
those in pressure transducers, weigh scales, and strain gage
applications.
The part can be configured to have two differential inputs or
four pseudo differential inputs that can be buffered or unbuffered.
Figure 18 shows the basic connections required to operate the part.
FILTER, OUTPUT DATA RATE, AND SETTLING TIME
A Σ-Δ ADC consists of a modulator followed by a digital filter.
The AD7192 has two filter options: a sinc
3
filter and a sinc
4
filter. The filter is selected using the SINC3 bit in the mode
register. When the SINC3 bit is set to 0 (default value), the sinc
4
filter is selected. The sinc
3
filter is selected when the SINC3 bit is
set to 1.
At low output data rates (<1 kHz), the noise-free resolution is
comparable for the two filter types. However, at the higher
update rates, the sinc
4
filter gives better noise-free resolution.
The sinc
4
filter also leads to better 50 Hz and 60 Hz rejection.
While the notch positions are not affected by the order of the
filter, the higher order filter has wider notches, which leads to
better rejection in the band (±1 Hz) around the notches. It also
gives better stop-band attenuation. The benefit of the sinc
3
filter
is its lower settling time for the same output data rate.
Chop Disabled
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
f
ADC
= f
CLK
/(1024 × FS[9:0])
where:
f
ADC
is the output data rate.
f
CLK
= master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to 4800 Hz;
that is, FS[9:0] can have a value from 1 to 1023.
The previous equation is valid for both the sinc
3
and sinc
4
filters. The settling time for the sinc
4
filter is equal to
t
SETTLE
= 4/f
ADC
and the settling time for the sinc
3
filter is equal to
t
SETTLE
= 3/f
ADC
Figure 19 and Figure 20 show the frequency response of the sinc
4
filter and sinc
3
filter, respectively, for an output data rate of 50 Hz.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0 255075100125150
FILTER GAIN (dB)
FREQUENCY (Hz)
07822-013
Figure 19. Sinc
4
Filter Response (50 Hz Output Data Rate)