Datasheet

AD7192
Rev. A | Page 23 of 40
Table 20. Channel Selection
Channel Enable Bits in the Configuration Register Channel Enabled
Status Register
Bits CHD[2:0]
Calibration
Register Pair
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
Positive Input
AIN(+)
Negative Input
AIN(−)
1 AIN1 AIN2 000 0
1 AIN3 AIN4 001 1
1 Temperature sensor 010 None
1 AIN2 AIN2 011 0
1 AIN1 AINCOM 100 0
1 AIN2 AINCOM 101 1
1 AIN3 AINCOM 110 2
1 AIN4 AINCOM 111 3
DATA REGISTER
(RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000)
The conversion result from the ADC is stored in this data
register. This is a read-only, 24-bit register. On completion of a
read operation from this register, the
RDY
pin/bit is set. When
the DAT_STA bit in the mode register is set to 1, the contents of
the status register are appended to each 24-bit conversion. This
is advisable when several analog input channels are enabled
because the three LSBs of the status register (CHD2 to CHD0)
identify the channel from which the conversion originated.
ID REGISTER
(RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xX0)
The identification number for the AD7192 is stored in the ID
register. This is a read-only register.