Datasheet
AD7192
Rev. A | Page 11 of 40
Pin No. Mnemonic Description
13 AIN3
Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with
AIN4 or as a pseudodifferential input when used with AINCOM.
14 AIN4
Analog Input. This pin can be configured as the negative input of a fully differential input pair when used
with AIN3 or as a pseudodifferential input when used with AINCOM.
15 REFIN1(+)
Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+)
can lie anywhere between AV
DD
and AGND + 1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is
AV
DD
, but the part functions with a reference from 1 V to AV
DD
.
16 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between AGND and AV
DD
− 1 V.
17 BPDSW Bridge Power-Down Switch to AGND.
18 AGND Analog Ground Reference Point.
19 DGND Digital Ground Reference Point.
20 AV
DD
Analog Supply Voltage, 3 V to 5.25 V. AV
DD
is independent of DV
DD
. Therefore, DV
DD
can be operated at 3 V with
AV
DD
at 5 V or vice versa.
21 DV
DD
Digital Supply Voltage, 2.7 V to 5.25 V. DV
DD
is independent of AV
DD
. Therefore, AV
DD
can be operated at 3 V
with DV
DD
at 5 V or vice versa.
22
SYNC
Logic input that allows for synchronization of the digital filters and analog modulators when using a number
of AD7192 devices. While SYNC
is low, the nodes of the digital filter, the filter control logic, and the
calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not
affect the digital interface but does reset RDY
to a high state if it is low. SYNC has a pull-up resistor internally
to DV
DD
.
23
DOUT/RDY
Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data output
pin to access the output shift register of the ADC. The output shift register can contain data from any of the
on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate
the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next
update occurs. The DOUT/RDY
falling edge can be used as an interrupt to a processor, indicating that valid
data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the
data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the
SCLK rising edge.
24 DIN
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control
registers in the ADC, with the register selection bits of the communications register identifying the
appropriate register.