4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA AD7192 FEATURES Temperature measurement Chromatography PLC/DCS analog input modules Data acquisition Medical and scientific instrumentation RMS noise: 11 nV @ 4.7 Hz (gain = 128) 15.5 noise-free bits @ 2.
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AD7192 TABLE OF CONTENTS Features .............................................................................................. 1 Offset Register ............................................................................ 24 Interface ............................................................................................. 1 Full-Scale Register ...................................................................... 24 Applications ....................................................................
AD7192 SPECIFICATIONS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = AVDD, REFINx(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter ADC Output Data Rate No Missing Codes2 Resolution RMS Noise and Output Data Rates Integral Nonlinearity Gain = 12 Gain > 1 Offset Error4, 5 Offset Error Drift vs. Temperature Offset Error Drift vs. Time Gain Error4 Gain Drift vs. Temperature Gain Drift vs.
AD7192 Parameter External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz 3 Sinc Filter Internal Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz ANALOG INPUTS Differential Input Voltage Ranges Absolute AIN Voltage Limits2 Unbuffered Mode Buffered Mode Analog Input Current Buffered Mode Input Current2 Input Current Drift Unbuffered Mode Input Current Input Current Drift REFERENCE INPUT REFIN Voltage Absolute REFIN Voltage Limits2 Average Reference Input Current AD7192B Unit T
AD7192 Parameter Average Reference Input Current Drift Normal Mode Rejection2 Common-Mode Rejection Reference Detect Levels TEMPERATURE SENSOR Accuracy Sensitivity BRIDGE POWER-DOWN SWITCH RON Allowable Current2 BURNOUT CURRENTS AIN Current DIGITAL OUTPUTS (P0 to P3) Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current2 Floating-State Output Capacitance INTERNAL/EXTERNAL CLOCK Internal Clock Frequency Duty Cycle External Clock/Cryst
AD7192 Parameter SYSTEM CALIBRATION2 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS 7 Power Supply Voltage AVDD − AGND DVDD − DGND Power Supply Currents AIDD Current DIDD Current IDD (Power-Down Mode) AD7192B Unit 1.05 × FS −1.05 × FS 0.8 × FS 2.1 × FS V max V min V min V max 3/5.25 2.7/5.25 V min/max V min/max 0.6 0.85 3.2 3.6 4.5 5 0.4 0.6 1.5 3 mA max mA max mA max mA max mA max mA max mA max mA max mA typ μA max 1 Test Conditions/Comments 1 0.
AD7192 TIMING CHARACTERISTICS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2.
AD7192 CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 07822-003 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev.
AD7192 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. Parameter AVDD to AGND DVDD to AGND AGND to DGND Analog Input Voltage to AGND Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND AIN/Digital Input Current Operating Temperature Range Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.
AD7192 MCLK1 1 24 DIN MCLK2 2 23 DOUT/RDY SCLK 3 22 SYNC CS 4 AD7192 21 DVDD P3 5 TOP VIEW (Not to Scale) 20 AVDD P2 6 19 DGND P1/REFIN2(+) 7 18 AGND P0/REFIN2(–) 8 17 BPDSW NC 9 16 REFIN1(–) AINCOM 10 15 REFIN1(+) AIN1 11 14 AIN4 AIN2 12 13 AIN3 NC = NO CONNECT 07822-005 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No.
AD7192 Pin No. 13 Mnemonic AIN3 14 AIN4 15 REFIN1(+) 16 17 18 19 20 REFIN1(−) BPDSW AGND DGND AVDD 21 DVDD 22 SYNC 23 DOUT/RDY 24 DIN Description Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN4 or as a pseudodifferential input when used with AINCOM. Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudodifferential input when used with AINCOM.
AD7192 45 8,388,882 40 8,388,880 35 8,388,878 30 8,388,876 8,388,874 25 20 8,388,872 15 8,388,870 10 8,388,868 5 8,388,866 0 200 400 600 800 1000 SAMPLE 0 8,388,850 8,388,870 8,388,890 8,388,910 07822-009 OCCURRENCE 8,388,884 07822-006 CODE TYPICAL PERFORMANCE CHARACTERISTICS 8,388,930 CODE Figure 9. Noise Distribution Histogram (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc4 Filter) Figure 6. Noise (VREF = AVDD = 5 V, Output Data Rate = 4.
AD7192 0.4 5 0.2 4 0 –0.2 OFFSET (µV) INL (ppm of FSR) 3 2 1 –0.4 –0.6 –0.8 0 –1.0 –1 –2 –1 0 1 2 3 4 VIN (V) –1.4 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 12. INL (Gain = 1) 07822-115 –3 07822-112 –2 –4 –1.2 Figure 15. Offset Error (Gain = 128, Chop Disabled) 20 1.000008 15 1.000006 1.000004 1.000002 5 1.000000 GAIN INL (ppm of FSR) 10 0 0.999998 0.999996 –5 0.999994 –10 0.999992 –15 –0.01 0 0.01 0.02 0.03 VIN (V) 0.
AD7192 RMS NOISE AND RESOLUTION The AD7192 has a choice of two filter types: sinc4 and sinc3. In addition, the AD7192 can be operated with chop enabled or chop disabled. The following tables show the rms noise of the AD7192 for some of the output data rates and gain settings with chop disabled and enabled for the sinc4 and sinc3 filters. The numbers given are for the bipolar input range with the external 5 V reference.
AD7192 SINC3 CHOP DISABLED Table 8. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 120 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 25 20 10 3.13 1.25 0.
AD7192 SINC4 CHOP ENABLED Table 10. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 Output Data Rate (Hz) 1.175 1.875 2.5 12.5 15 30 37.5 75 240 600 1200 Settling Time (ms) 1702 1067 800 160 133 66.7 53.3 26.7 8.33 3.33 1.
AD7192 SINC3 CHOP ENABLED Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 Output Data Rate (Hz) 1.56 2.5 3.33 16.6 20 40 50 100 320 800 1600 Settling Time (ms) 1282 800 600 120 100 50 40 20 6.25 2.5 1.
AD7192 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described on the following pages. In the following descriptions, “set” implies a Logic 1 state and “cleared” implies a Logic 0 state, unless otherwise noted. COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register.
AD7192 STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 16 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream.
AD7192 Table 17. Mode Register Bit Designations Bit Location MR23 to MR21 MR20 Bit Name MD2 to MD0 DAT_STA MR19, MR18 CLK1, CLK0 MR17, MR16 MR15 0 SINC3 MR14 MR13 0 ENPAR MR12 CLK_DIV MR11 SINGLE MR10 REJ60 MR9 to MR0 FS9 to FS0 Description Mode select bits. These bits select the operating mode of the AD7192 (see Table 18). This bit enables the transmission of status register contents after each data register read.
AD7192 Table 18. Operating Modes MD2 0 MD1 0 MD0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mode Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register go low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the communications register to 1, which enables continuous read.
AD7192 Table 19. Configuration Register Bit Designations Bit Location CON23 Bit Name CHOP CON22, CON21 CON20 0 REFSEL CON19 to CON16 CON15 to CON8 0 CH7 to CH0 CON7 BURN CON6 REFDET CON5 CON4 0 BUF CON3 U/B CON2 to CON0 G2 to G0 Description Chop enable bit. When the CHOP bit is cleared, chop is disabled. When the CHOP bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed.
AD7192 Table 20.
AD7192 GPOCON REGISTER (RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00) The GPOCON register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the general-purpose digital outputs. GP7 0(0) GP6 BPDSW(0) GP5 GP32EN(0) GP4 GP10EN(0) Table 21 outlines the bit designations for the GPOCON register. GP0 through GP7 indicate the bit locations. GP denotes that the bits are in the GPOCON register. GP7 denotes the first bit of the data stream.
AD7192 ADC CIRCUIT INFORMATION 5V REFIN1(+) AGND IN+ OUT+ OUT– IN– AIN1 AIN2 AIN3 AIN4 AINCOM MUX DVDD DGND AVDD REFERENCE DETECT AVDD Σ-Δ ADC PGA DOUT/RDY SERIAL INTERFACE AND CONTROL LOGIC DIN SCLK CS SYNC AGND TEMP SENSOR REFIN1(–) P3 P2 BPDSW AD7192 CLOCK CIRCUITRY MCLK1 MCLK2 07822-012 AGND P0/REFIN2(–) P1/REFIN2(+) Figure 18.
AD7192 0 The value of FS[9:0] can be varied from 1 to 1023. This results in an output data rate of 1.173 Hz to 1200 Hz for the sinc4 filter and 1.56 Hz to 1600 Hz for the sinc3 filter. The settling time for sinc3 or sinc4 is equal to –10 –30 tSETTLE = 2/fADC –40 Therefore, with chop enabled, the settling time is reduced for a given output data rate compared to the chop disabled mode.
AD7192 Normal mode rejection is one of the main functions of the digital filter. With chop disabled, 50 Hz rejection is obtained when the output data rate is set to 50 Hz, and 60 Hz rejection is achieved when the output data rate is set to 60 Hz. Simultaneous 50 Hz and 60 Hz rejection is obtained when the output data rate is set to 10 Hz. Simultaneous 50 Hz/60 Hz rejection can also be achieved using the REJ60 bit in the mode register.
AD7192 is 50 Hz (sinc4 filter); 50 Hz rejection is no longer achieved. The ADC must operate with an output data rate of 12.5 Hz to obtain 50 Hz rejection when zero latency is enabled. To obtain simultaneous 50 Hz/60 Hz rejection, the REJ60 bit in the mode register can be set when the output data rate is equal to 12.5 Hz. The stop-band attenuation is considerably reduced also (3 dB compared with 53 dB in the nonzero latency mode).
AD7192 line returns high after the first read operation. However, care must be taken to ensure that the read operations are completed before the next output update occurs. In continuous read mode, the data register can be read only once. The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY lines are used to communicate with the AD7192. The end of the conversion can be monitored using the RDY bit or pin.
AD7192 Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7192 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is completed. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, DOUT/RDY goes high.
AD7192 Continuous Read conversion is complete, and the new conversion is placed in the output serial register. Rather than write to the communications register each time a conversion is complete to access the data, the AD7192 can be configured so that the conversions are placed on the DOUT/ RDY line automatically.
AD7192 CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL The AD7192 has two differential/four pseudodifferential analog input channels, which can be buffered or unbuffered. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier.
AD7192 BURNOUT CURRENTS The common-mode range for these differential inputs is from AGND to AVDD. The reference input is unbuffered; therefore, excessive R-C source impedances introduce gain errors. The reference voltage REFIN (REFINx(+) − REFINx(−)) is AVDD nominal, but the AD7192 is functional with reference voltages from 1 V to AVDD.
AD7192 RESET TEMPERATURE SENSOR The circuitry and serial interface of the AD7192 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, whereas all on-chip registers are reset to their default values. A reset is automatically performed on power-up. When a reset is initiated, the user must allow a period of 500 μs before accessing any of the onchip registers.
AD7192 ENABLE PARITY The AD7192 also has a parity check function on chip that detects 1-bit errors in the serial communications between the ADC and the microprocessor. When the ENPAR bit in the mode register is set to 1, parity is enabled. The contents of the status register must be transmitted along with each 24-bit conversion when the parity function is enabled. To append the contents of the status register to each conversion read, the DAT_STA bit in the mode register should be set to 1.
AD7192 4.75 V, the gain error post internal full-scale calibration is 0.005%, typically. etch technique is generally best for ground planes because it gives the best shielding. When AVDD is less than 4.75 V, the CLK_DIV bit must be set when performing internal full-scale calibrations. The accuracy of the internal full-scale calibration is further increased if chop is enabled and a low output data rate is used while performing the calibration.
AD7192 APPLICATIONS INFORMATION measurements can be taken. In applications in which current consumption is being minimized, the AD7192 can be placed in standby mode, thus significantly reducing the power consumed in the application. In addition, the bridge power-down switch can be opened while in standby mode, thus avoiding unnecessary power consumption by the front-end transducer.
AD7192 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 33.
AD7192 NOTES Rev.
AD7192 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07822-0-5/09(A) Rev.
