Datasheet

AD7191
Rev. A | Page 6 of 20
TIMING CHARACTERISTICS
AV
DD
= 3 V to 5.25 V; DV
DD
= 2.7 V to 5.25 V; AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV
DD
, unless otherwise noted.
Table 2.
Parameter
1, 2
Limit at T
MIN
, T
MAX
(B Version) Unit Conditions/Comments
t
3
100 ns min SCLK high pulse width
t
4
100 ns min SCLK low pulse width
Read Operation
t
1
0 ns min
PDOWN falling edge to DOUT/RDY
active time
60 ns max DV
DD
= 4.75 V to 5.25 V
80 ns max DV
DD
= 2.7 V to 3.6 V
t
2
3
0 ns min SCLK active edge to data valid delay
4
60 ns max DV
DD
= 4.75 V to 5.25 V
80 ns max DV
DD
= 2.7 V to 3.6 V
t
5
5, 6
10 ns min Bus relinquish time after PDOWN inactive edge
80 ns max
t
6
0 ns min SCLK inactive edge to PDOWN inactive edge
t
7
10 ns min
SCLK inactive edge to DOUT/RDY
high
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 3.
3
These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
The SCLK active edge is the falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY
returns high after a read of the ADC. The digital word can be read only once.
I
SINK
(1.6mA WITH DV
DD
= 5V,
100µA WITH DV
DD
= 3V)
I
SOURCE
(200µA WITH DV
DD
= 5V,
100µA WITH DV
DD
= 3V)
1.6V
TO
OUTPUT
PIN
50pF
08163-002
Figure 2. Load Circuit for Timing Characterization
TIMING DIAGRAM
t
1
t
3
t
2
t
7
t
6
t
5
t
4
PDOWN (I)
NOTES
1. I = INPUT, O = OUTPUT
DOUT/RDY (O)
SCLK (I)
08163-003
Figure 3. Read Cycle Timing Diagram