Datasheet

AD7190 Data Sheet
Rev. C | Page 20 of 40
STATUS REGISTER
(RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80)
The status register is an 8-bit, read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 16 outlines the bit designations for the status
register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data
stream. The number in parentheses indicates the power-on/reset default status of that bit.
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RDY
(1) ERR(0) NOREF(0) Parity(0) 0(0) CHD2(0) CHD1(0) CHD0(0)
Table 16. Status Register Bit Designations
Bit Location Bit Name Description
SR7
RDY
Ready bit for the ADC. Cleared when data is written to the ADC data register. The
RDY
bit is set
automatically after the ADC data register is read, or a period of time before the data register is updated
with a new conversion result, to indicate to the user that the conversion data should not be read. It is also
set when the part is placed in power-down mode or idle mode or when
SYNC
is taken low.
The end of a conversion is also indicated by the DOUT/
RDY
pin. This pin can be used as an alternative to
the status register for monitoring the ADC for conversion data.
SR6 ERR ADC error bit. This bit is written to at the same time as the
RDY
bit. The ERR bit is set to indicate that the
result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange or
underrange or the absence of a reference voltage. The bit is cleared by a write operation to start a conversion.
SR5 NOREF No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a
voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is
cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled
by setting the REFDET bit in the configuration register to 1.
SR4 Parity Parity check of the data register. If the ENPAR bit in the mode register is set, the parity bit is set if there is an
odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data register. The
DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set,
the contents of the status register are transmitted along with the data for each data register read.
SR3 0 This bit will be set to 0.
SR2 to SR0 CHD2 to
CHD0
These bits indicate which channel corresponds to the data register contents. They do not indicate which
channel is presently being converted but indicate which channel was selected when the conversion
contained in the data register was generated.
MODE REGISTER
(RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060)
The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the
operating mode, the output data rate, and the clock source. Table 17 outlines the bit designations for the mode register. MR0 through
MR23 indicate the bit locations, MR denoting that the bits are in the mode register. MR23 denotes the first bit of the data stream. The
number in parentheses indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and
filter and sets the
RDY
bit.
MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16
MD2(0) MD1(0) MD0(0) DAT_STA(0) CLK1(1) CLK0(0) 0 0
MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8
Sinc3(0) 0 ENPAR(0) 0 Single(0) REJ60(0) FS9(0) FS8(0)
MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
FS7(0) FS6(1) FS5(1) FS4(0) FS3(0) FS2(0) FS1(0) FS0(0)