4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA AD7190 Data Sheet FEATURES Temperature measurement Chromatography PLC/DCS analog input modules Data acquisition Medical and scientific instrumentation RMS noise: 8.5 nV @ 4.7 Hz (gain = 128) 16 noise free bits @ 2.4 kHz (gain = 128) Up to 22.
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AD7190 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Full-Scale Register ...................................................................... 25 Applications ....................................................................................... 1 ADC Circuit Information.............................................................. 26 General Description ..........................................................
Data Sheet AD7190 SPECIFICATIONS AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, REFINx(+) = AVDD , REFINx(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter ADC Output Data Rate No Missing Codes2 Resolution RMS Noise and Output Data Rates Integral Nonlinearity B Grade WB Grade Offset Error4, 5 Offset Error Drift vs. Temperature5 Offset Error Drift vs. Time Gain Error4 B Grade WB Grade Gain Drift vs. Temperature Gain Drift vs.
AD7190 Data Sheet AD7190B Unit Test Conditions/Comments1 120 82 dB min dB min @ 50 Hz @ 60 Hz Sinc3 Filter Internal Clock @ 50 Hz, 60 Hz 120 120 dB min dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, REJ607 = 1, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, 50 ± 1 Hz. 60 Hz output data rate, 60 ± 1 Hz. 75 60 dB min dB min @ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz 70 70 dB min dB min 100 67 dB min dB min 95 95 dB min dB min ±VREF/gain V nom ±(AVDD – 1.
Data Sheet Parameter Normal Mode Rejection2 Common-Mode Rejection Reference Detect Levels TEMPERATURE SENSOR Accuracy Sensitivity BRIDGE POWER-DOWN SWITCH RON Allowable Current2 BURNOUT CURRENTS AIN Current DIGITAL OUTPUTS (P0 to P3) Output High Voltage, VOH2 Output Low Voltage, VOL2 Floating-State Leakage Current Floating-State Output Capacitance INTERNAL/EXTERNAL CLOCK Internal Clock Frequency Duty Cycle External Clock/Crystal2 Frequency Input Low Voltage, VINL Input High Voltage, VINH Input Current LOGIC
AD7190 Parameter POWER REQUIREMENTS8 Power Supply Voltage AVDD − AGND DVDD − DGND Power Supply Currents AIDD Current B Grade WB Grade DIDD Current IDD (Power-Down Mode) B Grade WB Grade Data Sheet AD7190B Unit 4.75/5.25 2.7/5.25 V min/max V min/max 1 1.3 4.5 4.75 6.2 6.75 5 5.3 6.8 7.4 0.4 0.6 1.5 mA max mA max mA max mA max mA max mA max mA max mA max mA max mA max mA max mA max mA typ 2 5 μA max μA max 1 Test Conditions/Comments1 0.85 mA typical, gain = 1, buffer off. 1.
Data Sheet AD7190 TIMING CHARACTERISTICS AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2.
AD7190 Data Sheet CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 07640-003 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev.
Data Sheet AD7190 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter AVDD to AGND Rating −0.3 V to +6.5 V DVDD to AGND AGND to DGND Analog Input Voltage to AGND −0.3 V to +6.5 V −0.3 V to +0.3 V −0.3 V to AVDD + 0.3 V Package Type 24-Lead TSSOP Reference Input Voltage to AGND Digital Input Voltage to DGND −0.3 V to AVDD + 0.
AD7190 Data Sheet MCLK1 1 24 DIN MCLK2 2 23 DOUT/RDY SCLK 3 22 SYNC CS 4 AD7190 21 DVDD P3 5 TOP VIEW (Not to Scale) 20 AVDD P2 6 19 DGND P1/REFIN2(+) 7 18 AGND P0/REFIN2(–) 8 17 BPDSW NC 9 16 REFIN1(–) AINCOM 10 15 REFIN1(+) AIN1 11 14 AIN4 AIN2 12 13 AIN3 NC = NO CONNECT 07640-005 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No.
Data Sheet Pin No. 13 Mnemonic AIN3 14 AIN4 15 REFIN1(+) 16 17 18 19 20 21 22 REFIN1(−) BPDSW AGND DGND AVDD DVDD SYNC 23 DOUT/RDY 24 DIN AD7190 Description Analog Input. It can be configured as the positive input of a fully differential input pair when used with AIN4 or as a pseudo differential input when used with AINCOM. Analog Input. It can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudo differential input when used with AINCOM.
AD7190 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 8,388,760 8,388,950 8,388,900 8,388,758 8,388,850 8,388,800 8,388,750 CODE 8,388,754 8,388,752 8,388,700 8,388,650 8,388,750 8,388,600 8,388,550 8,388,748 200 400 600 800 1000 SAMPLE Figure 6. Noise (VREF = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) 07640-106 0 8,388,450 0 100 200 300 400 500 600 700 800 900 1000 SAMPLES Figure 8.
Data Sheet AD7190 3.0 8,388,820 8,388,800 2.0 INL (ppm of FSR) 8,388,780 8,388,760 8,388,720 8,388,700 0 –1.0 8,388,680 –2.0 8,388,660 0 100 200 300 400 500 600 700 800 900 1000 SAMPLES –3.0 –2.5 07640-110 8,388,620 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 VIN (V) 07640-112 8,388,640 Figure 12. INL (Gain = 1) Figure 10.
AD7190 Data Sheet 66 1.000008 1.000007 1.000006 62 1.000005 GAIN OUTPUT VOLTAGE (µV) 64 60 1.000004 1.000003 58 1.000002 56 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 1.000000 –60 128.002 –0.2 128.001 –0.3 128.000 GAIN –0.1 –0.4 127.999 –0.5 127.998 –0.6 127.997 0 20 40 60 80 100 TEMERATURE (°C) 120 07640-115 OFFSET (µV) 128.003 –20 0 20 40 60 80 100 120 100 120 Figure 16.
Data Sheet AD7190 RMS NOISE AND RESOLUTION on a single channel. The effective resolution is also shown, and the output peak-to-peak (p-p) resolution, or noise-free resolution, is listed in parentheses. It is important to note that the effective resolution is calculated using the rms noise, wheras the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there is no code flicker. These numbers are typical and are rounded to the nearest ½ LSB.
AD7190 Data Sheet SINC3 CHOP DISABLED Table 8. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 20 10 3.125 1.25 0.625 Gain of 1 270 320 350 1000 1050 1500 1950 4000 56,600 442,000 Gain of 8 42 50 60 134 145 225 308 590 7000 55,000 Gain of 16 23 27 35 86 95 130 175 330 3500 28,000 Gain of 32 13.5 17 19 50 55 80 110 200 1800 14,000 Gain of 64 10.
Data Sheet AD7190 SINC4 CHOP ENABLED Table 10. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 1.175 1.875 2.5 12.5 15 37.5 75 240 600 1200 Settling Time (ms) 1702 1067 800 160 133 53 26.7 8.33 3.33 1.67 Gain of 1 177 219 234 637 686 1033 1343 2121 3536 10,200 Gain of 8 27 32 36 89 99 152 202 340 552 1360 Gain of 16 15 18 21 55 63 89 120 198 311 707 Gain of 32 8.5 11.5 13 32 37 53 71 124 198 389 Gain of 64 7 8.
AD7190 Data Sheet SINC3 CHOP ENABLED Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 1.56 2.5 3.33 16.6 20 50 100 320 800 1600 Settling Time (ms) 1282 800 600 120 100 40 20 6.25 2.5 1.25 Gain of 1 191 226 248 708 743 1061 1380 2829 40,100 312,550 Gain of 8 30 36 43 95 103 159 218 418 4950 38,540 Gain of 16 16.
Data Sheet AD7190 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described in the following sections. In the descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register.
AD7190 Data Sheet STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80) The status register is an 8-bit, read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 16 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register.
Data Sheet AD7190 Table 17. Mode Register Bit Designations Bit Location MR23 to MR21 MR20 Bit Name MD2 to MD0 DAT_STA MR19 to MR18 CLK1 to CLK0 MR17 to MR16 MR15 SINC3 MR14 MR13 ENPAR MR12 MR11 Single MR10 REJ60 MR9 to MR0 FS9 to FS0 Description Mode select bits. These bits select the operating mode of the AD7190 (see Table 18). This bit enables the transmission of status register contents after each data register read.
AD7190 Data Sheet Table 18. Operating Modes MD2 0 MD1 0 MD0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mode Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/ RDY pin and the RDY bit in the status register go low when a conversion is complete.
Data Sheet CON23 Chop(0) CON15 CH7(0) CON7 Burn(0) AD7190 CON22 0(0) CON14 CH6(0) CON6 REFDET(0) CON21 0(0) CON13 CH5(0) CON5 0(0) CON20 REFSEL(0) CON12 CH4(0) CON4 BUF(1) CON19 0(0) CON11 CH3(0) CON3 U/B (0) CON18 0(0) CON10 CH2(0) CON2 G2(1) CON17 0(0) CON9 CH1(0) CON1 G1(1) CON16 (0) CON8 CH0(1) CON0 G0(1) Table 19.
AD7190 Data Sheet Table 20.
Data Sheet GP7 0(0) GP6 BPDSW(0) AD7190 GP5 GP32EN(0) GP4 GP10EN(0) GP3 P3DAT(0) GP2 P2DAT(0) GP1 P1DAT(0) GP0 P0DAT(0) Table 21. Register Bit Designations Bit Location GP7 GP 6 Bit Name 0 BPDSW GP5 GP32EN GP4 GP10EN GP3 P3DAT GP2 P2DAT GP1 P1DAT GP0 P0DAT Description This bit must be programmed with a Logic 0 for correct operation. Bridge power-down switch control bit. This bit is set by the user to close the bridge power-down switch BPDSW to AGND. The switch can sink up to 30 mA.
AD7190 Data Sheet ADC CIRCUIT INFORMATION 5V REFIN1(+) AGND IN+ OUT+ OUT– IN– AVDD DVDD DGND AVDD AIN1 AIN2 AIN3 AIN4 AINCOM MUX Σ-Δ ADC PGA REFERENCE DETECT SERIAL INTERFACE AND CONTROL LOGIC DOUT/RDY DIN SCLK CS SYNC AGND TEMP SENSOR REFIN1(–) P3 P2 BPDSW AD7190 CLOCK CIRCUITRY MCLK1 MCLK2 07640-012 AGND P0/REFIN2(–) P1/REFIN2(+) Figure 18. Basic Connection Diagram OVERVIEW where: fADC is the output data rate. fCLK = master clock (4.92 MHz nominal).
Data Sheet AD7190 The value of FS[9:0] can be varied from 1 to 1023. This results in an output data rate of 1.173 Hz to 1200 Hz for the sinc4 filter and 1.56 Hz to 1600 Hz for the sinc3 filter. The settling time for the sinc3 or sinc4 filter is equal to 0 –10 –30 tSETTLE = 2/fADC –40 Therefore, with chop enabled, the settling time is reduced for a given output data rate compared to the chop disabled mode.
AD7190 Data Sheet 0 –10 –20 –30 –40 –50 –60 –70 Figure 23 and Figure 24 show the frequency response of the sinc4 and sinc3 filters, respectively, when the output data rate is programmed to 50 Hz and REJ60 is set to 1. –80 –90 –100 0 0 25 50 75 100 125 150 FREQUENCY (Hz) –20 Figure 25. Sinc4 Filter Response (12.
Data Sheet AD7190 is 50 Hz (sinc4 filter); 50 Hz rejection is no longer achieved. The ADC needs to operate with an output data rate of 12.5 Hz to obtain 50 Hz rejection when zero latency is enabled. To obtain simultaneous 50 Hz/60 Hz rejection, the REJ60 bit in the mode register can be set when the output data rate is equal to 12.5 Hz. The stop-band attenuation is considerably reduced also (3 dB compared with 53 dB in the nonzero latency mode).
AD7190 Data Sheet Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7190, with CS being used to decode the part. Figure 3 shows the timing for a read operation from the output shift register of the AD7190, and Figure 4 shows the timing for a write operation to the input shift register. It is possible to read the same word from the data register several times even though the DOUT/RDY line returns high after the first read operation.
Data Sheet AD7190 Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7190 converts continuously, the RDY bit in the status register going low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is completed. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data word has been read from the data register, DOUT/RDY goes high.
AD7190 Data Sheet Continuous Read conversion is complete and the new conversion is placed in the output serial register. Rather than write to the communications register each time a conversion is complete to access the data, the AD7190 can be configured so that the conversions are placed on the DOUT/ RDY line automatically.
Data Sheet AD7190 CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL The AD7190 has two differential/four pseudo differential analog input channels which can be buffered or unbuffered. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier.
AD7190 Data Sheet clock source is used, the clock source must be connected to the MCLK2 pin and the MCLK1 pin must be left floating. The internal clock can also be made available at the MCLK2 pin. This is useful when several ADCs are used in an application and the devices need to be synchronized. The internal clock from one device can be used as the clock source for all ADCs in the system.
Data Sheet AD7190 SYSTEM SYNCHRONIZATION TEMPERATURE SENSOR The SYNC input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the part. This allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of SYNC. SYNC needs to be taken low for four master clock cycles to implement the synchronization function. Embedded in the AD7190 is a temperature sensor.
AD7190 Data Sheet ENABLE PARITY The AD7190 also has a parity check function on-chip that detects 1-bit errors in the serial communications between the ADC and the microprocessor. When the ENPAR bit in the mode register is set to 1, parity is enabled. The contents of the status register must be transmitted along with each 24-bit conversion when the parity function is enabled. To append the contents of the status register to each conversion read, the DAT_STA bit in the mode register should be set to 1.
Data Sheet AD7190 The AD7190 gives the user access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and also to write its own calibration coefficients from prestored values in the EEPROM. A read of the registers can be performed at any time. However, the ADC must be placed in power-down or idle mode when writing to the registers. The values in the calibration registers are 24-bits wide.
AD7190 Data Sheet APPLICATIONS INFORMATION bridge power-down switch is connected in series with the cold side of the bridge. In normal operation, the switch is closed and measurements can be taken. In applications in which current consumption is being minimized, the AD7190 can be placed in standby mode, thus significantly reducing the power consumed in the application.
Data Sheet AD7190 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 33.
AD7190 Data Sheet NOTES ©2008–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07640-0-2/13(C) Rev.
