Datasheet

Data Sheet AD7176-2
Rev. A | Page 7 of 68
TIMING CHARACTERISTICS
IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, C
LOAD
= 20 pF, unless otherwise noted.
Table 2.
Parameter Limit at T
MIN
, T
MAX
(B Version) Unit Test Conditions/Comments
1, 2
t
3
25 ns min SCLK high pulse width
t
4
25 ns min SCLK low pulse width
READ OPERATION
t
1
0 ns min
CS
falling edge to DOUT/RDY active time
15 ns max IOVDD = 4.5 V to 5.5 V
40 ns max IOVDD = 2 V to 3.6 V
t
2
3
0 ns min SCLK active edge to data valid delay
4
12 ns max IOVDD = 4.5 V to 5.5 V
25 ns max IOVDD = 2 V to 3.6 V
t
5
5
2.5 ns min
Bus relinquish time after CS
inactive edge
20 ns max
t
6
0 ns min
SCLK inactive edge to CS
inactive edge
t
7
10 ns min
SCLK inactive edge to DOUT/RDY
high/low
WRITE OPERATION
t
8
0 ns min
CS
falling edge to SCLK active edge setup time
4
t
9
8 ns min Data valid to SCLK edge setup time
t
10
8 ns min Data valid to SCLK edge hold time
t
11
5 ns min
CS
rising edge to SCLK edge hold time
1
Sample tested during initial release to ensure compliance.
2
See Figure 2 and Figure 3.
3
The time required for the output to cross the V
OL
or V
OH
limits.
4
The SCLK active edge is the falling edge of SCLK.
5
RDY
returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while
RDY
is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the
digital word can be read only once.
TIMING DIAGRAMS
Figure 2. Read Cycle Timing Diagram
Figure 3. Write Cycle Timing Diagram
t
2
t
3
t
4
t
1
t
6
t
5
t
7
CS (I)
DOUT/RDY (O)
SCLK (I)
I = INPUT, O = OUTPUT
MSB LSB
11037-002
I = INPUT, O = OUTPUT
CS (I)
S
CLK (I)
DIN (I)
MSB LSB
t
8
t
9
t
10
t
11
11037-003