Datasheet

AD7176-2 Data Sheet
Rev. A | Page 62 of 68
FILTER CONFIGURATION REGISTER 3
Address: 0x2B, Reset: 0x0000, Name: FILTCON3
The Filter Configuration Registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers
resets any active ADC conversion and restarts converting at the first channel in the sequence.
Table 41. Bit Descriptions for FILTCON3
Bits Bit Name Settings Description Reset Access
15 SINC3_MAP3 If this bit is set, the mapping of the Filter Register changes to directly
program the decimation rate of the Sinc3 filter for Setup 3. All other
options are eliminated. This allows for fine tuning of the output data rate
and filter notch for rejection of specific frequencies. The data rate when on
a single channel equals FMOD/(32 × FILTCON3[14:0]).
0x0 RW
[14:12] RESERVED These bits are reserved and should be set to 0. 0x0 R
11 ENHFILTEN3 This bit enables various post filters for enhanced 50 Hz/60 Hz rejection for
Setup 3. The ORDER bits must be set to 00 to select the Sinc5 + Sinc1 filter
for this to work.
0x0 RW
0 Disabled
1 Enabled
[10:8] ENHFILT3 These bits select between various post filters for enhanced 50 Hz/60 Hz
rejection for Setup 3.
0x0 RW
010 27 SPS, 47 dB rejection, 36.7 ms settling
011 25 SPS, 62 dB rejection, 40 ms settling
101 20 SPS, 86 dB rejection, 50 ms settling
110 16.67 SPS, 92 dB rejection, 60 ms settling
7 RESERVED This bit is reserved and should be set to 0. 0x0 R
[6:5] ORDER3 These bits control the order of the digital filter that processes the
modulator data for Setup 3.
0x0 RW
00 Sinc5 + Sinc1 (default)
11 Sinc3
[4:0] ODR3 These bits control the output data rate of the ADC and, therefore, the
settling time and noise for Setup 3.
0x0 RW
00000 250,000
00001 125,000
00010 62,500
00011 50,000
00100 31,250
00101 25,000
00110 15,625
00111 10,000
01000 5000
01001 2500
01010 1000
01011 500
01100 397.5
01101
200
01110 100
01111 59.94
10000 49.96
10001 20
10010 16.667
10011 10
10100 5