Datasheet

Data Sheet AD7176-2
Rev. A | Page 5 of 68
Parameter Test Conditions/Comments Min Typ Max Unit
Turn-On Settling Time 100 nF capacitor 60 µs
Long-Term Stability
3
500 hours 460 ppm
Short Circuit I
SC
25 mA
EXTERNAL REFERENCE
Reference Input Voltage Reference input = (REF+) – (REF−) 1 2.5 AVDD1 V
Absolute Reference Input
Voltage Limits
1
AVSS − 0.05 AVDD1 + 0.05 V
Average Reference Input
Current
±72 µA/V
Average Reference Input
Current Drift
External clock ±1.2 nA/V/°C
Internal clock ±6 nA/V/°C
Normal Mode Rejection
1
See the Rejection parameter section
of this table
Common-Mode Rejection 83 dB
GENERAL-PURPOSE I/O (GPIO 0,
GPIO 1)
With respect to AVSS
Output High Voltage, V
OH
1
I
SOURCE
= 200 µA AVSS + 4 V
Output Low Voltage, V
OL
1
I
SINK
= 800 µA AVSS + 0.4 V
Input Mode Leakage Current
1
−10 +10 µA
Floating-State Output
Capacitance
5 pF
Input High Voltage, V
IH
1
AVSS + 3 V
Input Low Voltage, V
IL
1
AVSS + 0.7 V
CLOCK
Internal Clock
Frequency 16 MHz
Accuracy −2.5 +2.5 %
Duty Cycle 50:50 %
Output Low Voltage, V
OL
0.4 V
Output High Voltage, V
OH
0.8 × IOVDD V
Crystal
Frequency 14 16 16.384 MHz
Start-Up Time 50 µs
External Clock (CLKIO) 16 16.384 MHz
Duty Cycle
1
Typical duty cycle 50:50 (max:min) 30 50:50 70 %
LOGIC INPUTS
Input High Voltage, V
INH
1
2 V ≤ IOVDD ≤ 2.3 V 0.65 × IOVDD V
2.3 V ≤ IOVDD ≤ 5.5 V 0.7 × IOVDD V
Input Low Voltage, V
INL
1
2 V ≤ IOVDD ≤ 2.3 V 0.35 × IOVDD V
2.3 V ≤ IOVDD ≤ 5.5 V 0.7 V
Hysteresis
1
IOVDD > 2.7 V 0.08 0.25 V
IOVDD < 2.7 V 0.04 0.2 V
Leakage Currents −10 +10 µA
LOGIC OUTPUT (DOUT/RDY)
Output High Voltage, V
OH
1
IOVDD ≥ 4.5 V, I
SOURCE
= 1 mA 0.8 × IOVDD V
2.7 V ≤ IOVDD < 4.5 V, I
SOURCE
= 500 A 0.8 × IOVDD V
IOVDD < 2.7 V, I
SOURCE
= 200 A 0.8 × IOVDD V
Output Low Voltage, V
OL
1
IOVDD ≥ 4.5 V, I
SINK
= 2 mA 0.4 V
2.7 V ≤ IOVDD < 4.5 V, I
SINK
= 1 mA 0.4 V
IOVDD < 2.7 V, I
SINK
= 400 A 0.4 V
Leakage Current Floating state −10 +10 µA
Output Capacitance Floating state 10 pF