Datasheet

Data Sheet AD7176-2
Rev. A | Page 51 of 68
GPIO CONFIGURATION REGISTER
Address: 0x06, Reset: 0x0800, Name: GPIOCON
The GPIO Configuration Register controls the general-purpose I/O pins of the ADC.
Table 28. Bit Descriptions for GPIOCON
Bits Bit Name Settings Description Reset Access
[15:13] RESERVED These bits are reserved and should be set to 0. 0x0 R
12 MUX_IO This bit allows the ADC to control an external multiplexer, using GPIO0/GPIO1
in sync with the internal channel sequencing. The analog input pins used
for a channel can still be selected on a per channel basis. Therefore, it is
possible to have a 4-channel multiplexer in front of AIN0/AIN1 and another
in front of AIN2/AIN3, giving a total of eight differential channels with the
AD7175-2. However, only four channels at a time can be automatically
sequenced. A delay can be inserted after switching an external multiplexer
(see the DELAY bits in the ADC Mode Register).
0x0 RW
11 SYNC_EN This bit enables the
SYNC
/
ERROR
pin as a sync input. When set low, the
SYNC
/
ERROR
pin holds the ADC and filter in reset until
SYNC
/
ERROR
goes
high. An alternative operation of the
SYNC
/
ERROR
pin is available when
the ALT_SYNC bit in the Interface Mode Register is set. This mode only
works when multiple channels are enabled. In this case, a low on the
SYNC
/
ERROR
pin does not immediately reset the filter/modulator. Instead, if the
SYNC
/
ERROR
pin is low when the channel is due to be switched, the
modulator and filter are prevented from starting a new conversion.
Bringing
SYNC
/
ERROR
high begins the next conversion. This alternative
sync mode allows
SYNC
/
ERROR
to be used while cycling through channels.
0x1 RW
0 Disabled
1
Enabled
[10:9] ERR_EN These bits enable the
SYNC
/
ERROR
pin as an error input/output. 0x0 RW
00 Disabled
01
SYNC
/
ERROR
is an error input. The (inverted) readback state is OR'ed with
other error sources and is available in the ADC_ERROR bit in the Status
Register. The
SYNC
/
ERROR
pin state can also be read from the ERR_DAT bit
in this register.
10
SYNC
/
ERROR
is an open-drain error output. The Status Register error bits
are OR'ed, inverted, and mapped to the
SYNC
/
ERROR
pin.
SYNC
/
ERROR
pins of multiple devices can be wired together to a common pull-up
resistor so that an error on any device can be observed.
11
SYNC
/
ERROR
is a general-purpose output. The status of the pin is
controlled by the ERR_DAT bit in this register. This is referenced between
IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the
general-purpose I/O pins. It has an active pull-up in this case.
8 ERR_DAT This bit determines the logic level at the
ERROR
pin if the pin is enabled as
a general-purpose output. It reflects the readback status of the pin if the
pin is enabled as an input.
0x0 RW
[7:6] RESERVED These bits are reserved and should be set to 0. 0x0 R
5 IP_EN1 This bit turns GPIO1 into an input. Input should equal AVDD5 or AVSS. 0x0 RW
0 Disabled
1 Enabled
4 IP_EN0 This bit turns GPIO0 into an input. Input should equal AVDD5 or AVSS. 0x0 RW
0 Disabled
1 Enabled
3 OP_EN1 This bit turns GPIO1 into an output. Outputs are referenced between
AVDD1 and AVSS.
0x0 RW
0 Disabled
1 Enabled
2 OP_EN0 This bit turns GPIO0 into an output. Outputs are referenced between
AVDD1 and AVSS.
0x0 RW