Datasheet

Data Sheet AD7176-2
Rev. A | Page 49 of 68
INTERFACE MODE REGISTER
Address: 0x02, Reset: 0x0000, Name: IFMODE
The Interface Mode Register configures various serial interface options.
Table 25. Bit Descriptions for IFMODE
Bits Bit Name Settings Description Reset Access
[15:13] RESERVED These bits are reserved and should be set to 0. 0x0 R
12 ALT_SYNC This bit enables a different behavior of the
ERROR
\
SYNC
pin to allow the
use of
ERROR
\
SYNC
as a control for conversions when cycling channels
(see the description of the SYNC_EN bit in the
GPIO Configuration Register
for details).
0x0 RW
0 Disabled
1 Enabled
11 IOSTRENGTH This bit controls the drive strength of the DOUT pin. This bit should be set
when reading from the serial interface at high speed with low IOVDD
supply and moderate capacitance.
0x0 RW
0
Disabled (default)
1 Enabled
[10:9] RESERVED These bits are reserved and should be set to 0. 0x0 R
8 DOUT_RESET This bit prevents the DOUT/
RDY
pin from switching from outputting
DOUT to outputting
RDY
soon after the last rising edge of SCLK during a
read operation. Instead, the DOUT/
RDY
pin will continue to output the
LSB of the data until
CS
goes high. This allows for longer hold times for the
SPI master to sample the LSB of the data. When this bit is set,
CS
must not
be tied low.
0x0 RW
0 Disabled
1 Enabled
7 CONTREAD
This enables continuous read of the ADC data register. The ADC should be
configured in continuous conversion mode to use continuous read. For
more details, see the
Operating Modes section.
0x0 RW
0 Disabled
1 Enabled
6 DATA_STAT This enables the Status Register to be appended to the Data Register
when read so that channel and status information are transmitted with
the data. This is the only way to be sure that the channel bits read from
the Status Register correspond to the data in the Data Register.
0x0 RW
0 Disabled
1 Enabled
5 REG_CHECK This bit enables a register integrity checker, which can be used to monitor
any change in the value of the user registers. To use this feature, all other
registers should be configured as desired, with this bit cleared. Then write
to this register to set the REG_CHECK bit to 1. If the contents of any of the
registers change, the REG_ERROR bit is set in the Status Register. To clear
the error, the REG_CHECK bit should be set to 0. Neither the Interface
Mode Register nor the ADC Data or Status Register is included in the
registers that are checked. If a register needs to have a new value written,
this bit should first be cleared; otherwise, an error will be flagged falsely
when the new register contents are written.
0x0 RW
0 Disabled
1 Enabled
4 RESERVED This bit is reserved and should be set to 0. 0x0 R