Datasheet

AD7176-2 Data Sheet
Rev. A | Page 48 of 68
ADC MODE REGISTER
Address: 0x01, Reset: 0x8000, Name: ADCMODE
The ADC Mode Register controls the operating mode of the ADC and the master clock selection. A write to the ADC Mode Register
resets the filter and the
RDY
bits and starts a new conversion or calibration.
Table 24. Bit Descriptions for ADCMODE
Bits Bit Name Settings Description Reset Access
15 REF_EN Enables internal reference and outputs a buffered 2.5 V to the REFOUT pin. 0x1 RW
0 Disabled
1 Enabled
14 RESERVED This bit is reserved and should be set to 0. 0x0 R
13 SING_CYC This bit can be used when only a single channel is active to set the ADC to
only output at the settled filter data rate.
0x0 RW
0
Disabled
1 Enabled
[12:11] RESERVED These bits are reserved and should be set to 0. 0x0 R
[10:8] DELAY
These bits allow a programmable delay to be added after a channel switch
to allow for settling of external circuitry before the ADC starts processing
its input.
0x0 RW
000 0
001 4 µs
010 16 µs
011 40 µs
100 100 µs
101 200 µs
110
500 µs
111 1 ms
7
RESERVED
This bit is reserved and should be set to 0.
0x0
R
[6:4] MODE These bits control the operating mode of the ADC. Details can be found in
the Operating Modes section.
0x0 RW
000 Continuous Conversion Mode
001
Single Conversion Mode
010 Standby Mode
011 Power-Down Mode
100 Internal Offset Calibration
110 System Offset Calibration
111
System Gain Calibration
[3:2] CLOCKSEL This bit is used to select the ADC clock source. Selecting internal oscillator
also enables the internal oscillator.
0x0 RW
00
Internal oscillator
01 Internal oscillator output on XTAL2 pin
10 External clock input on XTAL2 pin
11 External crystal on XTAL1 and XTAL2 pins
[1:0] RESERVED These bits are reserved and should be set to 0. 0x0 R