Datasheet

Data Sheet AD7176-2
Rev. A | Page 43 of 68
GROUNDING AND LAYOUT
The analog inputs and reference inputs are differential and,
therefore, most of the voltages in the analog modulator are
common-mode voltages. The high common-mode rejection of
the part removes common-mode noise on these inputs. The
analog and digital supplies to the AD7176-2 are independent
and separately pinned out to minimize coupling between the
analog and digital sections of the device. The digital filter
provides rejection of broadband noise on the power supplies,
except at integer multiples of the master clock frequency.
The digital filter also removes noise from the analog and
reference inputs, provided that these noise sources do not
saturate the analog modulator. As a result, the AD7176-2 is
more immune to noise interference than a conventional high
resolution converter. However, because the resolution of the
AD7176-2 is high and the noise levels from the converter are so
low, care must be taken with regard to grounding and layout.
The printed circuit board (PCB) that houses the ADC must be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. A minimum etch
technique is generally best for ground planes because it results
in the best shielding.
In any layout, the user must keep in mind the flow of currents
in the system, ensuring that the paths for all return currents are as
close as possible to the paths the currents took to reach their
destinations.
Avoid running digital lines under the device because this
couples noise onto the die and allows the analog ground plane
to run under the AD7176-2 to prevent noise coupling. The
power supply lines to the AD7176-2 must use as wide a trace as
possible to provide low impedance paths and reduce glitches on
the power supply line. Shield fast switching signals like clocks
with digital ground to prevent radiating noise to other sections
of the board and never run clock signals near the analog inputs.
Avoid crossover of digital and analog signals. Run traces on
opposite sides of the board at right angles to each other. This
reduces the effects of feedthrough on the board. A microstrip
technique is by far the best but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes, whereas signals are
placed on the solder side.
Good decoupling is important when using high resolution ADCs.
The AD7176-2 has three power supply pins—AVDD1, AVDD2,
and IOVDD. The AVDD1 and AVDD2 pins are referenced to
AVSS, and the IOVDD pin is referenced to DGND. AVDD1 and
AVDD2 should be decoupled with a 10 μF tantalum capacitor
in parallel with a 0.1 μF capacitor to AVSS on each pin. The
0.1 μF capacitor should be placed as close as possible to the
device on each supply, ideally right up against the device.
IOVDD should be decoupled with a 10 μF tantalum capacitor
in parallel with a 0.1 μF capacitor to DGND. All analog inputs
should be decoupled to AVSS. If an external reference is used,
the REF+ and REF− pins should be decoupled to AVSS.
The AD7176-2 also has two on-board LDO regulators—one that
regulates the AVDD2 supply and one that regulates the IOVDD
supply. For the REGCAPA pin, it is recommended that 1 μF and
0.1 μF capacitors to AVSS be used. Similarly, for the REGCAPD
pin, it is recommended that 1 μF and 0.1 μF capacitors to
DGND be used.
If using the AD7176-2 for split supply operation, a separate
plane must be used for AVSS.