Datasheet

Data Sheet AD7176-2
Rev. A | Page 41 of 68
GENERAL-PURPOSE I/O
The AD7176-2 has two general-purpose digital input/output pins:
GPIO0 and GPIO1. These are enabled using the IP_EN0/IP_EN1
or OP_EN0/OP_EN1 bits in the GPIOCON register. When the
GPIO0 or GPIO1 pin is enabled as an input, the logic level at
the pin is contained in the DATA0 or DATA1 bit, respectively.
When the GPIO0 or GPIO1 pin is enabled as an output, the
GP_DATA0 or GP_DATA1 bits, respectively, determine the
logic level output at the pin. The logic levels for these pins are
referenced to AV DD1 and AVSS; therefore, outputs have an
amplitude of 5 V.
If an external multiplexer is used to increase the channel count,
the multiplexer logic pins can be controlled via the AD7176-2
GPIO pins. With the MUX_IO bit, the GPIOs timing is controlled
by the ADC; therefore, the channel change is synchronized with
the ADC, eliminating any need for external synchronization.
The
SYNC
/
ERROR
pin can also be used as a general-purpose
output. When ERR_EN bits in the GPIOCON register are set to
11, the
SYNC
/
ERROR
pin operates as a general-purpose output.
In this configuration, the ERR_DAT bit in the GPIOCON register
determines the logic level output at the pin. The logic level for the
pin is referenced to IOVDD and DGND, and the
SYNC
/
ERROR
pin has an active pull-up.
16-BIT/24-BIT CONVERSIONS
By default, the AD7176-2 generates 24-bit conversions. However,
the width of the conversions can be reduced to 16 bits. Setting
Bit WL16 in the interface mode register to 1 rounds all data
conversions to 16 bits. Clearing this bit sets the width of the
data conversions to 24 bits.
SERIAL INTERFACE RESET (DOUT_RESET)
The serial interface is reset when each read operation is
complete. The instant at which the serial interface is reset is
programmable. By default, the serial interface is reset after a
period of time following the last SCLK rising edge, the SCLK
edge on which the LSB is read by the processor. By setting Bit
DOUT_RESET in the interface mode register to 1, the instant at
which the interface is reset is controlled by the
CS
rising edge.
In this case, the DOUT/
RDY
pin continues to output the LSB of
the register being read until
CS
is taken high. Only on the
CS
rising edge is the interface reset. This configuration is useful if
the
CS
signal is used to frame all read operations. If
CS
is not
used to frame all read operations, DOUT_RESET should be set
to 0 so that the interface is reset following the last SCLK edge in
the read operation.
SYNCHRONIZATION (
SYNC
/
ERROR
)
Normal Synchronization
When the SYNC_EN bit in the GPIOCON register is set to 0,
the
SYNC
/
ERROR
pin functions as a synchronization pin. The
SYNC
input allows the user to reset the modulator and the
digital filter without affecting any of the setup conditions on
the part. This allows the user to start gathering samples of the
analog input from a known point in time, that is, the rising
edge of
SYNC
. This pin must be low for at least one master
clock cycle to ensure that synchronization occurs.
If multiple AD7176-2 devices are operated from a common
master clock, they can be synchronized so that their data registers
are updated simultaneously. This is normally done after each
AD7176-2 has performed its own calibration or has calibration
coefficients loaded into its calibration registers. A falling edge
on the
SYNC
pin resets the digital filter and the analog modulator
and places the AD7176-2 into a consistent known state. While
the
SYNC
pin is low, the AD7176-2 is maintained in this state.
On the
SYNC
rising edge, the modulator and filter are taken
out of this reset state, and on the next master clock edge, the
part starts to gather input samples again.
The part is taken out of reset on the master clock falling edge
following the
SYNC
low-to-high transition. Therefore, when
multiple devices are being synchronized, the
SYNC
pin should
be taken high on the master clock rising edge to ensure that all
devices begin sampling on the master clock falling edge. If the
SYNC
pin is not taken high in sufficient time, it is possible to
have a difference of one master clock cycle between the devices;
that is, the instant at which conversions are available differs
from part to part by a maximum of one master clock cycle.
The
SYNC
pin can also be used as a start conversion command.
In this mode, the rising edge of
SYNC
starts a conversion, and
the falling edge of
RDY
indicates when the conversion is complete.
The settling time of the filter has to be allowed for each data
register update.
Alternate Synchronization
Setting Bit ALT_SYNC in the interface mode register to 1 enables
an alternate synchronization scheme. The SYNC_EN bit in the
GPIOCON register must be set to 1 to enable this alternate scheme.
In this mode, the
SYNC
pin operates as a start conversion com-
mand when several channels of the AD7176-2 are enabled. When
SYNC
is taken low, the ADC completes the conversion on the
current channel, selects the next channel in the sequence, and
then waits until
SYNC
is taken high to commence the conversion.
The
RDY
pin goes low when the conversion is complete on
the current channel, and the data register is updated with the
corresponding conversion. Therefore, the
SYNC
command
does not interfere with the sampling on the currently selected
channel but allows the user to control the instant at which the
conversion begins on the next channel in the sequence.
The mode can be used only when several channels are enabled.
It is not recommended to use this mode when a single channel
is enabled.