Datasheet

AD7176-2 Data Sheet
Rev. A | Page 38 of 68
DIGITAL INTERFACE
The programmable functions of the AD7176-2 are via the SPI
serial interface. The serial interface of the AD7176-2 consists of
four signals:
CS
, DIN, SCLK, and DOUT/
RDY
. The DIN line is
used to transfer data into the on-chip registers, and DOUT/
RDY
is
used to access data from the on-chip registers. SCLK is the serial
clock input for the device, and all data transfers (either on DIN or
on DOUT/
RDY
) occur with respect to the SCLK signal.
The DOUT/
RDY
pin also functions as a data-ready signal, with
the line going low if
CS
is low when a new data-word is available
in the data register. The pin is reset high when a read operation
from the data register is complete. The DOUT/
RDY
pin also
goes high before updating the data register to indicate when not
to read from the device to ensure that a data read is not attempted
while the register is being updated.
CS
is used to select a device.
It can be used to decode the AD7176-2 in systems where several
components are connected to the serial bus.
Figure 2 and Figure 3 show timing diagrams for interfacing to
the AD7176-2 using
CS
to decode the part. Figure 2 shows the
timing for a read operation from the AD7176-2, and Figure 3
shows the timing for a write operation to the AD7176-2. It is
possible to read from the data register several times even though
the DOUT/
RDY
line returns high after the first read operation.
However, care must be taken to ensure that the read operations are
completed before the next output update occurs. In continuous
read mode, the data register can be read only once.
The serial interface can operate in 3-wire mode by tying
CS
low.
In this case, the SCLK, DIN, and DOUT/
RDY
lines are used to
communicate with the AD7176-2. The end of the conversion
can also be monitored using the
RDY
bit in the status register.
The serial interface can be reset by writing 64 SCLKs with
CS
=
0 and DIN = 1. A reset returns the interface to the state in which it
expects a write to the communications register. This operation
resets the contents of all registers to their power-on values.
Following a reset, allow a period of 500 μs before addressing the
serial interface.
CHECKSUM PROTECTION
The AD7176-2 has a checksum mode, which can be used to
improve interface robustness. Using the checksum ensures that
only valid data is written to a register and allows data read from
a register to be validated. If an error occurs during a register
write, the CRC_ERROR bit is set in the status register. However,
to ensure that the register write was successful, the register
should be read back and checksum verified.
For CRC checksum calculations during a write operation, the
following polynomial is always used:
x
8
+ x
2
+ x + 1
During read operations, the user can select between this
polynomial and a similar XOR function. The XOR function
requires less time to process on the host microcontroller than
the polynomial-based checksum. The CRC_EN bits in the
interface mode register enable and disable the checksum and
allow the user to select between the polynomial check and the
simple XOR check.
The checksum is appended to the end of each read and write
transaction. The checksum calculation for the write transaction
is calculated using the 8-bit command word and the 8- to 24-bit
data. For a read transaction, the checksum is calculated using
the command word and the 8- to 32-bit data output. Figure 50
and Figure 51 show SPI write and read transactions, respectively.
Figure 50. SPI Write Transaction with CRC
Figure 51. SPI Read Transaction with CRC
If checksum protection is enabled when continuous read mode
is active, there is an implied read data command of 0x44 before
every data transmission that needs to be accounted for when
calculating the checksum value. This ensures a nonzero checksum
value even if the ADC data equals 0x000000.
8-BIT COMMAND 8-BIT CRCUP TO 24-BIT INPUT
CS DATA CRC
CS
DIN
S
CLK
11037-074
8-BIT COMMAND 8-BIT CRCUP TO 32-BIT INPUT
CMD
DATA CRC
CS
DIN
SCLK
DOUT/
RDY
11037-075