Datasheet

Data Sheet AD7176-2
Rev. A | Page 37 of 68
STANDBY AND POWER-DOWN MODES
In standby mode, most blocks are powered down. The LDOs
remain active so that registers maintain their contents. The
internal reference remains active if enabled, and the crystal
oscillator remains active if selected. To power down the
reference in standby mode, set the REF_EN bit in the ADC
mode regsiter to 0. To power down the clock in standby mode,
set the CLOCKSEL bits in the ADC mode register to 00
(internal oscillator).
In power-down mode, all blocks are powered down, including
the LDOs. All registers lose their contents, and the GPIO outputs
are placed in tristate. To prevent accidental entry to power-down
mode, the ADC must first be placed into standby mode. Exiting
power-down mode requires 64 SCLKs with
CS
= 0 and DIN = 1,
that is, a serial interface reset. A delay of 500 µs is recommended
before issuing a subsequent serial interface command to allow
the LDO to power up.
CALIBRATION MODES
The AD7176-2 provides three calibration modes that can be
used to eliminate the offset and gain errors on a per setup basis:
• Internal zero-scale calibration mode
• System zero-scale calibration mode
• System full-scale calibration mode
Only one channel can be active during calibration. After each
conversion, the ADC conversion result is scaled using the ADC
calibration registers before being written to the data register.
The default value of the offset register is 0x800000, and the
nominal value of the gain register is 0x555555. The calibration
range of the ADC gain is from 0.4 × V
REF
to 1.05 × V
REF
. The
following equations show the calculations that are used. In
unipolar mode, the ideal relationship—that is, not taking into
account the ADC gain error and offset error—is as follows:
2
0x400000
)0x800000(2
75.
0
23
×
×






−−×
×
=
Gain
Offset
V
V
Data
REF
IN
In bipolar mode, the ideal relationship—that is, not taking into
account the ADC gain error and offset error—is as follows:
0x800000
0x400000
0x800000)(2
0.75
23
+×






−
−×
×
=
Gain
Offset
V
V
Data
REF
IN
To start a calibration, write the relevant value to the MODE bits
in the ADC mode register. The DOUT/
RDY
pin and the RDY bit
in the status register go high when the calibration initiates. When
the calibration is complete, the contents of the corresponding
offset or gain register are updated, the
RDY
bit in the status
register is reset, the DOUT/
RDY
pin returns low (if
CS
is low),
and the
AD7176-2 reverts to standby mode.
During an internal offset calibration, the selected positive
analog input pin is disconnected, and both modulator inputs
are connected internally to the selected negative analog input
pin. For this reason, it is necessary to ensure that the voltage on
the selected negative analog input pin does not exceed the
allowed limits and is free from excessive noise and interference.
System calibrations, however, expect the system zero-scale
(offset) and system full-scale (gain) voltages to be applied to the
ADC pins before initiating the calibration modes. As a result,
errors external to the ADC are removed.
From an operational point of view, treat a calibration like
another ADC conversion. An offset calibration, if required,
must always be performed before a full-scale calibration. Set the
system software to monitor the RDY bit in the status register or
the DOUT/
RDY
pin to determine the end of a calibration via a
polling sequence or an interrupt-driven routine. All calibrations
require a time equal to the settling time of the selected filter and
output data rate to be completed.
An internal offset calibration, system zero-scale calibration, and
system full-scale calibration can be performed at any output data
rate. Using lower output data rates results in better calibration
accuracy and is accurate for all output data rates. A new calibration
is required for a given channel if the reference source for that
channel is changed.
The offset error is typically ±40 µV and an offset calibration
reduces the offset error to the order of the noise. The gain error
is factory calibrated at ambient temperature. Following this
calibration, the gain error is typically ±0.001%.
The AD7176-2 provides the user with access to the on-chip
calibration registers, allowing the microprocessor to read the
calibration coefficients of the device and to write its own
calibration coefficients. A read or write of the offset and gain
registers can be performed at any time except during an internal
or self-calibration.