Datasheet

Data Sheet AD7176-2
Rev. A | Page 29 of 68
SINC3 FILTER
The Sinc3 filter achieves the best single-channel noise performance
at lower rates and is, therefore, most suitable for single-channel
applications. The Sinc3 filter always has a settling time equal to
t
SETTLE
= 3/Output Data Rate
Figure 36 shows the frequency domain filter response for the
Sinc3 filter. The Sinc3 filter has good roll-off over frequency
and has wide notches for good notch frequency rejection.
Figure 36. Sinc3 Filter Response
The output data rates with the accompanying settling time and
rms noise for the Sinc3 filter are shown in Table 19.
It is possible to finely tune the output data rate for the Sinc3 filter by
setting the SINC3_MAP bit in the filter configuration register. If
this bit is set, the mapping of the filter register changes to directly
program the decimation rate of the Sinc3 filter. All other options
are eliminated. The data rate when on a single channel can be
calculated using the following equation:
4:0]FILTCONx[1
f
RateDataOutput
MOD
×
=
32
where:
f
MOD
is the modulator rate and is 8 MHz.
FILTCONx[14:0] are the contents on the filter configuration
register excluding the MSB.
For example, an output data rate of 50 SPS can be achieved with
SINC3_MAP enabled by setting the FILTCONx[14:0] bits to a
value of 5000.
SINGLE CYCLE SETTLING
The AD7176-2 can be configured by setting the SING_CYC bit
in the ADC mode register so that only fully settled data is output,
thus effectively putting the ADC into a single cycle settling mode.
This mode achieves single cycle settling by reducing the output
data rate to be equal to the settling time of the ADC for the selected
output data rate. This bit has no effect with the Sinc5 + Sinc1 at
output data rates of 10 kSPS and lower.
Figure 37 shows a step on the analog input with this mode
disabled and the Sinc3 filter selected. It takes at least three
cycles after the step change for the output to reach the final
settled value.
Figure 37. Step Input Without Single Cycle Settling
Figure 38 shows the same step on the analog input but with
single cycle settling enabled. It takes at least a single cycle for
the output to be fully settled. The output data rate is now
reduced to equal the settling time of the filter at the selected
output data rate.
Figure 38. Step Input with Single Cycle Settling
0
–120
0 150100
50
FILTER GAIN (dB)
FREQUENCY (Hz)
11037-060
–100
–80
–60
–40
–20
–110
–90
–70
–50
–30
–10
1/ODR
ANALOG
INPUT
FULLY
SETTLED
ADC
OUTPUT
11037-061
t
SETTLE
ANALOG
INPUT
FULLY
SETTLED
ADC
OUTPUT
11037-062