Datasheet

Data Sheet AD7176-2
Rev. A | Page 27 of 68
Internal Reference
The AD7176-2 includes its own low noise, low drift voltage
reference. The internal reference has a 2.5 V output. The internal
reference is output on the REFOUT pin after the REF_EN bit in
the ADC mode register is set and is decoupled to AVSS with a
0.1 µF capacitor. The AD7176-2 internal reference is enabled by
default on power-up and is selected as the reference source for
the ADC.
The REFOUT signal is buffered prior to being output to the pin.
The signal can be used externally in the circuit as a common-mode
source for external amplifier configurations. This is shown in
Figure 30 in the Driver Amplifiers section, where the REFOUT
pin supplies the VOCM input of the AD8475 amplifier.
AD7176-2 CLOCK SOURCE
The AD7176-2 requires a master clock of 16 MHz. The AD7176-2
can source its sampling clock from one of three scenarios:
• Internal oscillator
• External crystal
• External clock source
All output data rates listed in the data sheet relate to a master
clock rate of 16 MHz. Using a lower clock frequency from, for
instance, an external source will scale any listed data rate
proportionally. To achieve the specified data rates, particularly
rates for rejection of 50 Hz and 60 Hz, a 16 MHz clock should
be used. The source of the master clock is selected by setting the
CLOCKSEL bits (Bits[3:2]) in the ADC mode register as shown
in Table 17. The default operation on power-up and reset of the
AD7176-2 is to operate with the internal oscillator.
Internal Oscillator
The internal oscillator runs at 16 MHz and can be used as the
ADC master clock. It is the default clock source for the AD7176-2
and is specified with an accuracy of ±2.5%.
There is an option to allow the internal clock oscillator to be
output on the AD7176-2 CLKIO/XTAL2 pin. The clock output
is driven to the IOVDD logic level. Use of this option can affect
the dc performance of the AD7176-2 due to the disturbance
introduced by the output driver. The extent to which the
performance is affected depends on the IOVDD voltage supply.
Higher IOVDD voltages create a wider logic output swing from
the driver and affect performance to a greater extent. This is
further exaggerated if the IOSTRENGTH bit is set at higher
IOVDD levels (see Table 25 for more information).
External Crystal
If higher precision, lower jitter clock sources are required, the
AD7176-2 has the ability to use an external crystal to generate
the master clock. The crystal is connected to the XTAL1 and
XTAL2 pins. A recommended crystal for use is the FA-20H—a
16 MHz, 10 ppm, 9 pF crystal from Epson-Toyocom—which is
available in a surface-mounted package. As shown in Figure 33,
allow for two capacitors to be inserted from the traces
connecting the crystal to the XTAL1 and XTAL2 pins. These
capacitors allow for circuit tuning. Connect these capacitors to
the DGND pin. The value for these capacitors depends on the
length and capacitance of the trace connections between the
crystal and the XTAL1 and XTAL2 pins. Therefore, the values
of these capacitors differ depending on the PCB layout and the
crystal employed. As a result, empirical testing of the circuit is
required.
Figure 33. External Crystal Connections
External Clock
The AD7176-2 can also use an externally supplied clock. In
systems where this is desirable, the external clock is routed to
the CLKIO pin. In this configuration, the CLKIO pin accepts
the externally sourced clock and routes it to the modulator. The
logic level of this clock input is defined by the voltage applied to
the IOVDD pin.
1
1037-160
9
10
Cx1
Cx2
XTAL1
CLKIO/XTAL2
*DECOUPLE
TO DGND.
AD7176-2
*
*