24-Bit, 250 kSPS Sigma-Delta ADC with 20 µs Settling AD7176-2 Data Sheet FEATURES GENERAL DESCRIPTION Fast and flexible output rate—5 SPS to 250 kSPS Fast settling time—20 µs Channel scan data rate of 50 kSPS/channel Performance specifications 17 noise free bits at 250 kSPS 20 noise free bits at 2.5 kSPS 22 noise free bits at 5 SPS INL ±2.
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AD7176-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface Reset (DOUT_RESET) .................................. 41 Applications ....................................................................................... 1 Synchronization (SYNC/ERROR) ........................................... 41 General Description .........................................................................
Data Sheet AD7176-2 REVISION HISTORY 4/13—Rev. 0 to Rev. A Changes to Table 20 ........................................................................31 11/12—Revision 0—Initial Version Rev.
AD7176-2 Data Sheet SPECIFICATIONS AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock = 16 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter ADC SPEED AND PERFORMANCE Output Data Rate (ODR) No Missing Codes1 Resolution Noise Noise Free Resolution ACCURACY Integral Nonlinearity (INL) Offset Error2 Offset Drift Offset Drift vs. Time3 Gain Error2 Gain Drift vs. Temperature1 Gain Drift vs.
Data Sheet Parameter Turn-On Settling Time Long-Term Stability3 Short Circuit EXTERNAL REFERENCE Reference Input Voltage Absolute Reference Input Voltage Limits1 Average Reference Input Current Average Reference Input Current Drift Normal Mode Rejection1 Common-Mode Rejection GENERAL-PURPOSE I/O (GPIO 0, GPIO 1) Output High Voltage, VOH1 Output Low Voltage, VOL1 Input Mode Leakage Current1 Floating-State Output Capacitance Input High Voltage, VIH1 Input Low Voltage, VIL1 CLOCK Internal Clock Frequency Accur
AD7176-2 Parameter SYSTEM CALIBRATION1 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS Power Supply Voltage AVDD1 − AVSS AVDD2 – AVSS AVSS – DGND IOVDD − DGND IOVDD – AVSS POWER SUPPLY CURRENTS Full Operating Mode AVDD1 Current AVDD2 Current IOVDD Current Standby Mode Standby (LDO On) Power-Down Mode POWER DISSIPATION Full Operating Mode Standby Mode Power-Down Mode Data Sheet Test Conditions/Comments Min Typ −1.05 × FS 0.8 × FS 4.5 2 −2.
Data Sheet AD7176-2 TIMING CHARACTERISTICS IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, CLOAD = 20 pF, unless otherwise noted. Table 2. Parameter t3 t4 READ OPERATION t1 t23 t55 t6 t7 WRITE OPERATION t8 t9 t10 t11 Limit at TMIN, TMAX (B Version) 25 25 Unit ns min ns min Test Conditions/Comments1, 2 SCLK high pulse width SCLK low pulse width 0 15 40 0 12 25 2.
AD7176-2 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. θJA is specified for a device soldered on a JEDEC test board for surface-mount packages. The values listed in Table 4 are based on simulated data.
Data Sheet AD7176-2 AIN4 1 24 AIN3 REF– 2 23 AIN2 REF+ 3 22 AIN1 REFOUT 4 21 AIN0 REGCAPA 5 20 GPIO1 19 GPIO0 18 REGCAPD AVDD2 8 17 DGND XTAL1 9 16 IOVDD CLKIO/XTAL2 10 15 SYNC/ERROR DOUT/RDY 11 14 CS DIN 12 13 SCLK AVSS 6 AVDD1 7 AD7176-2 TOP VIEW (Not to Scale) 11037-004 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No.
AD7176-2 Pin No. 15 Mnemonic SYNC/ERROR 16 IOVDD 17 18 DGND REGCAPD 19 20 21 22 23 24 GPIO0 GPIO1 AIN0 AIN1 AIN2 AIN3 Data Sheet Description Can be switched between a logic input and a logic output in the GPIOCON register. When synchronization input is enabled, this pin allows for synchronization of the digital filters and analog modulators when using multiple AD7176-2 devices.
Data Sheet AD7176-2 TYPICAL PERFORMANCE CHARACTERISTICS 450 8388358 400 8388357 350 OCCURENCE ADC CODE 300 8388356 8388355 250 200 150 100 8388354 0 100 200 300 400 0 11037-005 8388353 500 SAMPLE 8388354 8388356 8388356 ADC CODE Figure 5. Noise (AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, VREF = 5 V, Output Data Rate = 5 SPS) 11037-008 50 Figure 8. Noise Distribution Histogram (AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.
AD7176-2 Data Sheet 0 12 –20 250kSPS 10 AMPLITUDE (dB) 6 4 –100 –140 1kSPS 2 3 4 5 VCM (V) –160 11037-012 0 1 –80 –120 10kSPS 2 0 –60 0 5k 10k 15k 20k 25k FREQUENCY (Hz) 11037-019 RMS NOISE (µV) –40 8 Figure 14. 1 kHz Input Tone, −0.5 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, VREF = 2.5 V, Output Data Rate = 50 kSPS) Figure 11. Noise vs. Common-Mode Input Voltage (AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, VREF = 2.5 V) 11.0 0 –20 10.5 10.
AD7176-2 0 –20 –20 –40 –40 –60 –60 –80 –100 –80 –100 –120 –120 –140 –140 –160 0 20k 40k 60k 80k 100k 120k FREQUENCY (Hz) –160 10 30 20 50 40 60 70 FREQUENCY (Hz) Figure 17. 1 kHz Input Tone, −0.5 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, VREF = 2.5 V, Output Data Rate = 250 kSPS) 11037-031 CMRR (dB) 0 11037-023 AMPLITUDE (dB) Data Sheet Figure 20. Common-Mode Rejection Ratio (10 Hz to 70 Hz) (AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.
Data Sheet 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 11037-034 POWER SUPPLY REJECTION (dB) AD7176-2 Figure 23. Power Supply Rejection Ratio vs. Frequency (AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V) Rev.
Data Sheet AD7176-2 NOISE PERFORMANCE AND RESOLUTION Table 6 shows the rms noise and the noise free (peak-to-peak) resolution of the AD7176-2 for various output data rates and filters. The numbers given are for the bipolar input range with an external 5 V reference. on a single channel. It is important to note that the peak-topeak resolution is calculated based on the peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker.
AD7176-2 Data Sheet GETTING STARTED The AD7176-2 includes a precision 2.5 V low drift (2 ppm/°C) band gap internal reference. This reference can be selected to be used for the ADC conversions, reducing the external component count. Alternatively, the reference can be output to the REFOUT pin to be used as a low noise biasing voltage for the external circuitry. An example of this is using the REFOUT signal to set the input common mode for an external driving amplifier.
Data Sheet AD7176-2 The AD7176-2 can be used across a wide variety of applications, providing high resolution and accuracy. A sample of these scenarios is as follows: • • • Fast scanning of analog input channels using the internal multiplexer. Fast scanning of analog input channels using an external multiplexer. High resolution at lower speeds in either channel scanning or ADC per channel applications.
AD7176-2 Data Sheet Reading the ID register is the recommended method for verifying correct communication with the part. The ID registers is a read only register and contains the value 0x0C9X for the AD7176-2. The communication register and ID register details are described in Table 7 and Table 8. Table 7. Communications Register Reg 0x00 Name COMMS Bits [7:0] Bit 7 WEN Bit 6 R/W Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RA Reset 0x00 RW W Table 8.
Data Sheet AD7176-2 CONFIGURATION OVERVIEW Figure 28 provides an overview of the configuration flow, divided into the following three blocks: • • ADC and interface mode configuration (labeled A in Figure 28) ADC setups (labeled B in Figure 28) Channel map configuration (labeled C in Figure 28) A WRITE TO ADC MODE REGISTER AND INTERFACE MODE REGISTER; SET UP HIGH LEVEL ADC PERIPHERALS AND INTERFACE B SET UP CONFIGURATION; FOUR POSSIBLE ADC SETUPS USING DEDICATED FILTER, OFFSET, AND GAIN REGISTERS C
AD7176-2 Data Sheet ADC and Interface Mode Configuration enable bits. The reference select bits are contained in the setup configuration registers (see the ADC Setups section for more information). The ADC mode register and the interface mode register (see Block A in Figure 28) configure the core peripherals to be used by the AD7176-2 and the mode for the digital interface. Interface Mode Register ADC Mode Register The interface mode register is used to configure the digital interface operation.
Data Sheet AD7176-2 reference, an external reference connected between REF+ and REF− pins, or AVDD1 – AVSS. ADC Setups The AD7176-2 has four independent setups (see Block B in Figure 28). Each setup consists of the following four registers: • • • • Filter Configuration Register The filter configuration register is used to select which digital filter is used at the output of the ADC modulator. The order of the filter and the output data rate is selected by setting the bits in this register.
AD7176-2 Data Sheet Channel Map Configuration The AD7176-2 has four independent channels (see Block C in Figure 28). The user can select which of the four setups is used for each channel. This allows for per channel configuration. Channel Map Register The channel map register is used to select which of the five analog input pins are used as either the positive analog input or the negative analog input for that channel.
Data Sheet AD7176-2 CIRCUIT DESCRIPTION ANALOG INPUT Fully Differential Inputs The AD7176-2 has five analog input pins: AIN0, AIN1, AIN2, AIN3, and AIN4. Each of these pins connects to the internal crosspoint multiplexer. The crosspoint multiplexer enables any of these inputs to be configured as an input pair, either pseudo differential or fully differential. The AD7176-2 can have up to four active channels. When more than one channel is enabled, the channels are automatically sequenced in order.
AD7176-2 Data Sheet AD8475 with a fixed common mode of 2.5 V. The output of the AD8475 amplifier is connected to an RC network. The RC network, as shown in Figure 30, includes RIN = 10 Ω; C1, C2 = 270 pF; and C3 = 680 pF. The RC circuit acts to provide the dynamic charge required by the AD7176-2 switched sampling capacitors while isolating the amplifier output from any kickback from the dynamic switched capacitor input.
Data Sheet AD7176-2 AD8656 The AD8656 is a low noise, dual precision CMOS amplifier. The AD8656 allows the user to connect a signal of interest directly to a high impedance, low noise, low offset amplifier input that can drive the AD7176-2 switched capacitor input. The AD8656 can operate from a single 5 V supply. When using an external 5 V reference such as the ADR445 in conjunction with the AD7176-2, the AD8656 output can swing to within −1 dBFS (which equates to a differential input of ±4.
AD7176-2 Data Sheet ADA4940 are recommended for use. The external reference should be applied to the AD7176-2 reference pins as shown in Figure 32. The output of any external reference should be decoupled to AVSS. As shown in Figure 32, the ADR445 output is decoupled with a 0.1 μF capacitor at its output for stability purposes. The output is then connected to a 4.7 μF capacitor, which acts as a reservoir for any dynamic charge required by the ADC, and followed by a 0.
Data Sheet AD7176-2 The AD7176-2 includes its own low noise, low drift voltage reference. The internal reference has a 2.5 V output. The internal reference is output on the REFOUT pin after the REF_EN bit in the ADC mode register is set and is decoupled to AVSS with a 0.1 µF capacitor. The AD7176-2 internal reference is enabled by default on power-up and is selected as the reference source for the ADC. The REFOUT signal is buffered prior to being output to the pin.
AD7176-2 Data Sheet DIGITAL FILTERS to control the final ADC output data rate. Figure 35 shows the frequency domain response of the Sinc5 + Sinc1 filter at a 50 SPS output data rate. The Sinc5 + Sinc1 filter has a slow roll-off over frequency and narrow notches. The AD7176-2 has three flexible filter options to allow for optimization of noise, settling time, and rejection: Sinc5 + Sinc1 filter Sinc3 filter Enhanced 50 Hz and 60 Hz rejection filters 0 –20 Figure 34.
Data Sheet AD7176-2 SINC3 FILTER For example, an output data rate of 50 SPS can be achieved with SINC3_MAP enabled by setting the FILTCONx[14:0] bits to a value of 5000. The Sinc3 filter achieves the best single-channel noise performance at lower rates and is, therefore, most suitable for single-channel applications. The Sinc3 filter always has a settling time equal to tSETTLE = 3/Output Data Rate Figure 36 shows the frequency domain filter response for the Sinc3 filter.
AD7176-2 Data Sheet Table 19. AD7176-2 Output Data Rate (ODR), Noise, Settling Time (tSETTLE), and Rejection Using the Sinc3 Filter Output Data Rate (SPS) 1 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 400 200 100 59.94 49.96 20 16.667 10 5 1 2 Settling Time (ms)1 0.012 0.024 0.048 0.060 0.096 0.120 0.192 0.300 0.600 1.200 3.000 6.000 7.500 15.000 30.000 50.004 60.000 150.000 180.000 300.000 600.
Data Sheet AD7176-2 ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS The enhanced filters are designed to provide rejection of 50 Hz and 60 Hz simultaneously and to allow the user to trade off settling time and rejection. These filters can operate up to 27.27 SPS or can reject up to 90 dB of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz interference. These filters are realized by post filtering the output of the Sinc5 + Sinc1 filter. For this reason, the Sinc5 + Sinc1 filter must be selected when using the enhanced filters.
Data Sheet 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –60 –70 –80 –80 –90 –90 –100 –100 40 300 400 500 600 0 –10 –20 –20 –30 –30 FILTER GAIN (dB) 0 –40 –50 –60 –80 –90 –90 70 FREQUENCY (Hz) –100 11037-064 65 0 –10 –10 –20 –20 –30 –30 FILTER GAIN (dB) 0 –50 –60 –90 –90 500 FREQUENCY (Hz) 600 11037-065 –80 400 500 600 –60 –70 300 400 –50 –80 200 300 –40 –70 100 200 Figure 43.
AD7176-2 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –40 –50 –60 –70 –70 –80 –80 –90 –90 –100 –100 40 0 100 200 300 400 500 600 FREQUENCY (Hz) Figure 45. DC to 600 Hz,16.667 SPS ODR, 60 ms Settling Time 45 50 55 FREQUENCY (Hz) 60 65 70 11037-070 FILTER GAIN (dB) 0 11037-069 FILTER GAIN (dB) Data Sheet Figure 46. Zoom in 40 Hz to 70 Hz, 16.667 SPS ODR, 60 ms Settling Time Rev.
AD7176-2 Data Sheet OPERATING MODES CONTINUOUS CONVERSION MODE Continuous conversion is the default power-up mode. The AD7176-2 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is complete. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register.
Data Sheet AD7176-2 CONTINUOUS READ MODE To enable continuous read mode, set the CONTREAD bit in the interface mode register. When this bit is set, the only serial interface operations possible are reads from the data register. To exit continuous read mode, issue a dummy read of the ADC data register command (0x44) while RDY is low. Alternatively, apply a software reset, that is, 64 SCLKs with CS = 0 and DIN = 1. This resets the ADC and all register contents.
AD7176-2 Data Sheet SINGLE CONVERSION MODE In single conversion mode, the AD7176-2 performs a single conversion and is placed in standby mode after the conversion is complete. DOUT/RDY goes low to indicate the completion of a conversion. When the data-word has been read from the data register, DOUT/RDY goes high. The data register can be read several times, if required, even when DOUT/RDY has gone high.
Data Sheet AD7176-2 STANDBY AND POWER-DOWN MODES In standby mode, most blocks are powered down. The LDOs remain active so that registers maintain their contents. The internal reference remains active if enabled, and the crystal oscillator remains active if selected. To power down the reference in standby mode, set the REF_EN bit in the ADC mode regsiter to 0. To power down the clock in standby mode, set the CLOCKSEL bits in the ADC mode register to 00 (internal oscillator).
AD7176-2 Data Sheet DIGITAL INTERFACE The DOUT/RDY pin also functions as a data-ready signal, with the line going low if CS is low when a new data-word is available in the data register. The pin is reset high when a read operation from the data register is complete. The DOUT/RDY pin also goes high before updating the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. CS is used to select a device.
Data Sheet AD7176-2 CRC CALCULATION Polynomial The checksum, which is 8-bits wide, is generated using the polynomial x8 + x2 + x + 1 To generate the checksum, the data is left shifted by eight bits to create a number ending in eight Logic 0s. The polynomial is aligned so that its MSB is adjacent to the leftmost Logic 1 of the data. An XOR (exclusive OR) function is applied to the data to produce a new, shorter number.
AD7176-2 Data Sheet XOR Calculation The checksum, which is 8-bits wide, is generated by splitting the data into bytes and then performing an XOR of the bytes. Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) Using the previous example, Divide into three bytes: 0x65, 0x43, and 0x21 01100101 0x65 01000011 0x43 00100110 XOR result 00100001 0x21 00000111 CRC Rev.
Data Sheet AD7176-2 GENERAL-PURPOSE I/O The AD7176-2 has two general-purpose digital input/output pins: GPIO0 and GPIO1. These are enabled using the IP_EN0/IP_EN1 or OP_EN0/OP_EN1 bits in the GPIOCON register. When the GPIO0 or GPIO1 pin is enabled as an input, the logic level at the pin is contained in the DATA0 or DATA1 bit, respectively. When the GPIO0 or GPIO1 pin is enabled as an output, the GP_DATA0 or GP_DATA1 bits, respectively, determine the logic level output at the pin.
AD7176-2 Data Sheet ERROR FLAGS The status register contains three error bits—ADC_ERROR, CRC_ERROR, and REG_ERROR—that flag errors with the ADC conversion, errors with the CRC check, and errors due to changes in the registers, respectively. In addition, the ERROR pin can indicate that an error has occurred. ADC_ERROR The ADC_ERROR bit in the status register flags any errors that occur during the conversion process. The flag is set when an overvoltage or undervoltage occurs on the analog inputs.
Data Sheet AD7176-2 GROUNDING AND LAYOUT The analog inputs and reference inputs are differential and, therefore, most of the voltages in the analog modulator are common-mode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog and digital supplies to the AD7176-2 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device.
AD7176-2 Data Sheet REGISTER SUMMARY Table 21.
Data Sheet Reg Name 0x38 GAIN0 AD7176-2 Bits Bit 7 [23:16] [15:8] [7:0] 0x39 GAIN1 [23:16] [15:8] [7:0] 0x3A GAIN2 [23:16] [15:8] [7:0] 0x3B GAIN3 [23:16] [15:8] [7:0] Bit 6 Bit 5 Bit 4 Bit 3 GAIN0[23:16] GAIN0[15:8] Bit 2 Bit 1 Bit 0 Reset RW 0x5XXXX0 RW GAIN0[7:0] GAIN1[23:16] GAIN1[15:8] 0x5XXXX0 RW GAIN1[7:0] GAIN2[23:16] GAIN2[15:8] 0x5XXXX0 RW GAIN2[7:0] GAIN3[23:16] GAIN3[15:8] GAIN3[7:0] Rev.
AD7176-2 Data Sheet REGISTER DETAILS COMMUNICATIONS REGISTER Address: 0x00, Reset: 0x00, Name: COMMS Table 22. Bit Descriptions for COMMS Bits 7 Bit Name WEN 6 R/W Settings 0 1 [5:0] RA 000000 000001 000010 000011 000100 000110 000111 010000 010001 010010 010011 100000 100001 100010 100011 101000 101001 101010 101011 110000 110001 110010 110011 111000 111001 111010 Description This bit must be low to begin communications with the ADC.
Data Sheet AD7176-2 STATUS REGISTER Address: 0x00, Reset: 0x80, Name: STATUS The Status Register is an 8-bit register that contains ADC and serial interface status information. It can optionally be appended to the Data Register by setting the DATA_STAT bit in the Interface Mode Register. Table 23.
AD7176-2 Data Sheet ADC MODE REGISTER Address: 0x01, Reset: 0x8000, Name: ADCMODE The ADC Mode Register controls the operating mode of the ADC and the master clock selection. A write to the ADC Mode Register resets the filter and the RDY bits and starts a new conversion or calibration. Table 24.
Data Sheet AD7176-2 INTERFACE MODE REGISTER Address: 0x02, Reset: 0x0000, Name: IFMODE The Interface Mode Register configures various serial interface options. Table 25. Bit Descriptions for IFMODE Bits [15:13] 12 Bit Name RESERVED ALT_SYNC Settings 0 1 11 IOSTRENGTH 0 1 [10:9] 8 RESERVED DOUT_RESET 0 1 7 CONTREAD 0 1 6 DATA_STAT 0 1 5 REG_CHECK 0 1 4 RESERVED Description These bits are reserved and should be set to 0.
AD7176-2 Bits [3:2] Bit Name CRC_EN Data Sheet Settings 00 01 10 1 0 RESERVED WL16 0 1 Description Enables CRC protection of register reads/writes. CRC increases the number of bytes in a serial interface transfer by one. See the CRC Calculation section for more details. Disabled. XOR checksum enabled for register read transactions. Register writes will still use CRC with these bits set. CRC checksum enabled for read and write transactions. This bit is reserved and should be set to 0.
Data Sheet AD7176-2 GPIO CONFIGURATION REGISTER Address: 0x06, Reset: 0x0800, Name: GPIOCON The GPIO Configuration Register controls the general-purpose I/O pins of the ADC. Table 28. Bit Descriptions for GPIOCON Bits [15:13] 12 Bit Name RESERVED MUX_IO 11 SYNC_EN Settings 0 1 [10:9] ERR_EN 00 01 10 11 8 ERR_DAT [7:6] 5 RESERVED IP_EN1 0 1 4 IP_EN0 0 1 3 OP_EN1 0 1 2 OP_EN0 Description These bits are reserved and should be set to 0.
AD7176-2 Bits Bit Name Data Sheet Settings 0 1 1 0 GP_DATA1 GP_DATA0 Description Disabled Enabled This bit is the readback or write data for GPIO1. This bit is the readback or write data for GPIO0. Reset Access 0x0 0x0 RW RW Reset 0x0C9X Access R ID REGISTER Address: 0x07, Reset: 0x0C9X, Name: ID The ID register returns a 16-bit ID. For the AD7176-2, this should be 0x0C94. Table 29.
Data Sheet AD7176-2 CHANNEL MAP REGISTER 0 Address: 0x10, Reset: 0x8001, Name: CHMAP0 The Channel Map Registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for each channel, and which setup should be used to configure the ADC for that channel. Table 30.
AD7176-2 Data Sheet CHANNEL MAP REGISTER 1 Address: 0x11, Reset: 0x0001, Name: CHMAP1 The Channel Map Registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for each channel, and which setup should be used to configure the ADC for that channel. Table 31.
Data Sheet AD7176-2 CHANNEL MAP REGISTER 2 Address: 0x12, Reset: 0x0001, Name: CHMAP2 The Channel Map Registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for each channel, and which setup should be used to configure the ADC for that channel. Table 32.
AD7176-2 Data Sheet CHANNEL MAP REGISTER 3 Address: 0x13, Reset: 0x0001, Name: CHMAP3 The Channel Map Registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for each channel, and which setup should be used to configure the ADC for that channel. Table 33.
Data Sheet AD7176-2 SETUP CONFIGURATION REGISTER 0 Address: 0x20, Reset: 0x1020, Name: SETUPCON0 The Setup Configuration Registers are 16-bit registers that configure the reference selection and output coding of the ADC. Table 34. Bit Descriptions for SETUPCON0 Bits [15:13] 12 Bit Name RESERVED BI_UNIPOLAR0 Settings 0 1 [11:6] [5:4] RESERVED REF_SEL0 00 10 11 [3:0] RESERVED Description These bits are reserved and should be set to 0. This bit sets the output coding of the ADC for Setup 0.
AD7176-2 Data Sheet SETUP CONFIGURATION REGISTER 2 Address: 0x22, Reset: 0x1020, Name: SETUPCON2 The Setup Configuration Registers are 16-bit registers that configure the reference selection and output coding of the ADC. Table 36. Bit Descriptions for SETUPCON2 Bits [15:13] 12 Bit Name RESERVED BI_UNIPOLAR2 Settings 0 1 [11:6] [5:4] RESERVED REF_SEL2 00 10 11 [3:0] RESERVED Description These bits are reserved and should be set to 0. This bit sets the output coding of the ADC for Setup 2.
Data Sheet AD7176-2 FILTER CONFIGURATION REGISTER 0 Address: 0x28, Reset: 0x0000, Name: FILTCON0 The Filter Configuration Registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets any active ADC conversion and restarts converting at the first channel in the sequence. Table 38.
AD7176-2 Data Sheet FILTER CONFIGURATION REGISTER 1 Address: 0x29, Reset: 0x0000, Name: FILTCON1 The Filter Configuration Registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets any active ADC conversion and restarts converting at the first channel in the sequence. Table 39.
Data Sheet AD7176-2 FILTER CONFIGURATION REGISTER 2 Address: 0x2A, Reset: 0x0000, Name: FILTCON2 The Filter Configuration Registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets any active ADC conversion and restarts converting at the first channel in the sequence. Table 40.
AD7176-2 Data Sheet FILTER CONFIGURATION REGISTER 3 Address: 0x2B, Reset: 0x0000, Name: FILTCON3 The Filter Configuration Registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets any active ADC conversion and restarts converting at the first channel in the sequence. Table 41.
Data Sheet AD7176-2 OFFSET REGISTER 0 Address: 0x30, Reset: 0x800000, Name: OFFSET0 The Offset (Zero-Scale) Registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system. Table 42. Bit Descriptions for OFFSET0 Bits [23:0] Bit Name OFFSET0 Settings Description Offset calibration coefficient for Setup 0.
AD7176-2 Data Sheet GAIN REGISTER 0 Address: 0x38, Reset: 0x5xxxx0, Name: GAIN0 The Gain (Full-Scale) Registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system. Table 46. Bit Descriptions for GAIN0 Bits [23:0] Bit Name GAIN0 Settings Description Gain calibration coefficient for Setup 0.
Data Sheet AD7176-2 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 52.
AD7176-2 Data Sheet NOTES Rev.
Data Sheet AD7176-2 NOTES Rev.
AD7176-2 Data Sheet NOTES ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11037-0-4/13(A) Rev.
