Datasheet

Data Sheet AD7171
Rev. A | Page 5 of 16
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.25 V,, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = V
DD
, unless otherwise noted.
Table 2.
Parameter
1, 2
Limit at T
MIN
, T
MAX
Unit Conditions/Comments
READ
t
1
100 ns min SCLK high pulse width
t
2
100 ns min SCLK low pulse width
t
3
3
0 ns min SCLK active edge to data valid delay
4
60 ns max V
DD
= 4.75 V to 5.25 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
4
10 ns min
SCLK inactive edge to DOUT/RDY
high
RESET
t
5
100 ns min
PDRST
low pulse width
t
6
25 ms typ
PDRST
high to data valid delay
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 3.
3
These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
SCLK active edge is the falling edge of SCLK.
I
SINK
(1.6mA WITH V
DD
= 5V,
100µA WITH V
DD
= 3V)
I
SOURCE
(200µA WITH V
DD
= 5V,
100µA WITH V
DD
= 3V)
1.6V
TO
OUTPUT
PIN
50pF
08417-002
Figure 2. Load Circuit for Timing Characterization
TIMING DIAGRAMS
t
3
t
1
t
2
t
4
DOUT/RDY (O)
SCLK (I)
I = INPUT, O = OUTPUT
MSB LSB
08417-003
Figure 3. Read Cycle Timing Diagram
t
5
t
6
PDRST (I)
DOUT/RDY (O)
I = INPUT, O = OUTPUT
08417-004
Figure 4. Resetting the AD7171