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16-Bit Low Power Sigma-Delta ADC

Data Sheet

AD7171

Rev. A Document Feedback

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FEATURES

Output data rate: 125 Hz

Pin-programmable power-down and reset

Status function

Internal clock oscillator

Current: 135 µA

Power supply: 2.7 V to 5.25 V

–40°C to +105°C temperature range

Package: 10-lead 3 mm x 3 mm LFCSP

INTERFACE

2-wire serial (read-only device)

SPI compatible

Schmitt trigger on SCLK

APPLICATIONS

Weigh scales

Pressure measurement

Industrial process control

Portable instrumentation

FUNCTIONAL BLOCK DIAGRAM

16-BIT Σ-Δ

ADC

AD7171

GND

INTERNAL

CLOCK

REFIN(+)

AIN(+)

AIN(–)

REFIN(–)

DOUT/RDY

SCLK

PDRST

08417-001

Figure 1.

Table 1.

REF

= V

RMS Noise P-P Noise

P-P

Resolution ENOB

5 V 11.5 μV 76 μV 16 bits 16 bits

3 V 6.9 μV 45 μV 16 bits 16 bits

GENERAL DESCRIPTION

The AD7171 is a very low power 16-bit analog-to-digital converter

(ADC). It contains a precision 16-bit sigma-delta (Σ-Δ) ADC

and an on-chip oscillator. Consuming only 135 µA, the AD7171

is particularly suitable for portable or battery operated products

where very low power is a requirement. The AD7171 also has a

power-down mode in which the device consumes 5 μA, thus

increasing the battery life of the product.

For ease-of-use, all the features of the AD7171 are controlled by

dedicated pins. Each time a data read occurs, eight status bits

are appended to the 16-bit conversion. These status bits contain

a pattern sequence that can be used to confirm the validity of

the serial transfer.

The output data rate of the AD7171 is 125 Hz, whereas the

settling time is 24 ms. The AD7171 has one differential input

and a gain of 1. This is useful in applications where the user

needs to use an external amplifier to implement system-specific

filtering or gain requirements.

The AD7171 operates with a power supply from 2.7 V to 5.25 V.

It is available in a 10-lead LFCSP package.

The AD7170 is a 12-bit version of the AD7171. It has the same

feature set as the AD7171 and is pin-for-pin compatible.

Summary of content (16 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAM Output data rate: 125 Hz Pin-programmable power-down and reset Status function Internal clock oscillator Current: 135 µA Power supply: 2.7 V to 5.25 V –40°C to +105°C temperature range Package: 10-lead 3 mm x 3 mm LFCSP GND VDD AIN(+) REFIN(+) REFIN(–) DOUT/RDY 16-BIT Σ-Δ ADC AIN(–) AD7171 SCLK INTERNAL CLOCK PDRST 08417-001 Data Sheet 16-Bit Low Power Sigma-Delta ADC AD7171 Figure 1. INTERFACE Table 1.
PAGE 2
AD7171 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Overview ..................................................................................... 10 Interface ............................................................................................. 1 Filter, Data Rate, and Settling Time ......................................... 10 Applications .................................................................
PAGE 3
Data Sheet AD7171 SPECIFICATIONS VDD = 2.7 V to 5.25 V, VREF = VDD, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter ADC CHANNEL Output Data Rate (fADC) No Missing Codes 2 Resolution Peak-to-Peak (p-p) Effective Resolution (ENOB) RMS Noise Integral Nonlinearity Offset Error Offset Error Drift vs. Temperature Full-Scale Error Gain Drift vs.
PAGE 4
AD7171 Parameter LOGIC OUTPUT (DOUT/RDY) Output High Voltage, VOH2 Data Sheet Min AD7171B 1 Typ IDD (Power-Down/Reset Mode) 1 2 3 Unit Test Conditions/Comments 0.4 0.4 V V V V µA pF VDD = 3 V, ISOURCE = 100 µA VDD = 5 V, ISOURCE = 200 µA VDD = 3 V, ISINK = 100 µA VDD = 5 V, ISINK = 1.6 mA 5.25 V 130 150 µA µA µA VDD − 0.
PAGE 5
Data Sheet AD7171 TIMING CHARACTERISTICS VDD = 2.7 V to 5.25 V,, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted. Table 2. Parameter1, 2 READ t1 t2 t33 Limit at TMIN, TMAX Unit Conditions/Comments t4 100 100 0 60 80 10 ns min ns min ns min ns max ns max ns min SCLK high pulse width SCLK low pulse width SCLK active edge to data valid delay4 VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.
PAGE 6
AD7171 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.
PAGE 7
Data Sheet AD7171 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 DOUT/RDY 2 AD7171 9 AIN(+) 3 8 VDD AIN(–) 4 TOP VIEW (Not to Scale) 7 GND REFIN(+) 5 6 REFIN(–) 10 NC NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO GROUND. 08417-005 PDRST Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic SCLK 2 DOUT/RDY 3 4 5 AIN(+) AIN(−) REFIN(+) 6 7 8 9 REFIN(−) GND VDD PDRST 10 NC EPAD Description Serial Clock Input.
PAGE 8
AD7171 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.025 10 VREF = VDD = 5V 8 0.023 GAIN ERROR (%) 6 4 0.019 0.017 2 –10 20 50 80 110 TEMPERATURE (°C) 0.015 –40 08417-015 0 –40 0.021 –10 20 50 80 110 TEMPERATURE (°C) Figure 6. AD7171 RMS Noise vs. Temperature 08417-008 RMS NOISE (µV) VREF = VDD = 3V Figure 9. Gain Error vs. Temperature 140 0.266 0.200 132 VREF = VDD = 5V 0.066 IDD (µA) INL (LSB) 0.133 0 124 116 –0.
PAGE 9
Data Sheet AD7171 OUTPUT NOISE AND RESOLUTION SPECIFICATIONS Table 6 shows the rms noise of the AD7171. The numbers given are for a 5 V and a 3 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. The corresponding p-p resolution is also listed along with the effective resolution (ENOB). It is important to note that the effective resolution is calculated using the rms noise, whereas the p-p resolution is based on the p-p noise.
PAGE 10
AD7171 Data Sheet ADC CIRCUIT INFORMATION OVERVIEW POWER-DOWN/RESET(PDRST) The AD7171 is a low power ADC that incorporates a precision 16-bit Σ-Δ modulator and an on-chip digital filter intended for measuring wide dynamic range, low frequency signals. The device has an internal clock and one differential input. It operates with an output data rate of 125 Hz and has a gain of 1. A 2-wire interface simplifies data retrieval from the AD7171. The PDRST pin functions as a power-down pin and a reset pin.
PAGE 11
Data Sheet AD7171 DATA OUTPUT CODING The AD7171 uses offset binary coding. Therefore, a negative full-scale voltage results in a code of 000...000, a zero differential input voltage results in a code of 100...000, and a positive fullscale input voltage results in a code of 111...111. The output code for any analog input voltage can be represented as DOUT/RDY pin is dual purpose: it functions as a data ready pin and as a data out pin.
PAGE 12
AD7171 Data Sheet GROUNDING AND LAYOUT Because the analog input and reference input of the ADC are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejection of the part removes common-mode noise on these inputs. The digital filter provides rejection of broadband noise on the power supply, except at integer multiples of the modulator sampling frequency.
PAGE 13
Data Sheet AD7171 APPLICATIONS INFORMATION SIGNAL CONDITIONING CIRCUIT Figure 14 shows the AD7171 used in a signal conditioning circuit for a single-ended analog input. In a low side shunt current monitor, a low resistance shunt resistor converts the current to voltage. The resulting voltage is amplified and applied to the AD7171. 32kΩ TEMPERATURE SYSTEM 1kΩ Figure 13 shows the AD7171 used in a temperature measurement system.
PAGE 14
AD7171 Data Sheet OUTLINE DIMENSIONS 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 1 5 BOTTOM VIEW TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.30 0.25 0.20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 MIN PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF 02-05-2013-C PIN 1 INDEX AREA Figure 15.
PAGE 15
Data Sheet AD7171 NOTES Rev.