Datasheet

AD7156
Rev. 0 | Page 5 of 28
TIMING SPECIFICATIONS
V
DD
= 1.8 V to 3.6 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = V
DD
, temperature range = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
CONVERTER
Conversion Time
1
20 ms Both channels, 10 ms per channel.
Wake-Up Time from Power-Down Mode
2, 3
0.3 ms
Power-Up Time
2, 4
2 ms
Reset Time
2, 5
2 ms
SERIAL INTERFACE
6, 7
See Figure 2.
SCL Frequency 0 400 kHz
SCL High Pulse Width, t
HIGH
0.6 µs
SCL Low Pulse Width, t
LOW
1.3 µs
SCL, SDA Rise Time, t
R
0.3 µs
SCL, SDA Fall Time, t
F
0.3 µs
Hold Time (Start Condition), t
HD;STA
0.6 µs After this period, the first clock is generated.
Setup Time (Start Condition), t
SU;STA
0.6 µs Relevant for repeated start condition.
Data Setup Time, t
SU;DAT
0.1 µs
Setup Time (Stop Condition), t
SU;STO
0.6 µs
Data Hold Time (Master), t
HD;DAT
10 ns
Bus-Free Time (Between Stop and Start Conditions), t
BUF
1.3 µs
1
Conversion time is 304 internal clock cycles for both channels (nominal clock 16 kHz); the internal clock frequency is equal to the specified excitation frequency.
2
Specification is not production tested but is supported by characterization data at initial product release.
3
Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion.
4
Power-up time is the maximum delay between the V
DD
crossing the minimum level (1.8 V) and either the start of conversion or when ready to receive a serial
interface command.
5
Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial
interface command.
6
Sample tested during initial release to ensure compliance.
7
All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
P
S
t
LOW
t
R
t
F
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STA
t
HD;STA
t
SU;STO
t
HIGH
SCL
PS
SDA
07726-002
t
BUF
Figure 2. Serial Interface Timing Diagram