Datasheet

AD7156
Rev. 0 | Page 17 of 28
DATA REGISTERS
Ch 1 Address Pointer 0x01, Address Pointer 0x02
Ch 2 Address Pointer 0x03, Address Pointer 0x04
16 Bits, Read Only
Default Value 0x0000
Data from the last complete capacitance-to-digital conversion
reflects the capacitance on the input. Only the 12 MSBs of the
data registers are used for the CDC result. The 4 LSBs are
always 0, as shown in Figure 36.
The data register is updated after a finished conversion on the
capacitive channel, with one exception: when the serial interface
read operation from the data register is in progress, the data
register is not updated and the new capacitance conversion
result is lost.
The stop condition on the serial interface is considered to be
the end of the read operation. Therefore, to prevent incorrect
data reading through the serial interface, the two bytes of a
data register should be read sequentially using the register
address pointer autoincrement feature of the serial interface.
The nominal AD7156 CDC transfer function (an ideal transfer
function excluding offset and/or gain error) maps the input
capacitance between zero scale and full scale to output data
codes between 0x3000 and 0xD000 only (see Table 8).
For an ideal part, linear, with no offset error and no gain error,
the input capacitance can be calculated from the output data
using the following equation:
(pF)_
960,40
288,12
pF)( RangeInput
Data
C ×
−
=
where Input_Range = 4 pF, 2 pF, 1 pF, or 0.5 pF.
The following is the same equation written with hexadecimal
numbers:
(pF)_
000xA0
3000x0
pF)( RangeInput
Data
C ×
−
=
With offset error and gain error included, the equation is:
)pF(_
%100
(%)_
1
(pF)_
960,40
288,12
pF)(
ErrorOffset
ErrorGain
RangeInput
Data
C
+
⎟
⎠
⎞
⎜
⎝
⎛
+
××
−
=
Or the same equation with hexadecimal numbers:
)pF(_
%100
(%)_
1
(pF)_
000xA0
3000
x
0
pF)(
ErrorOffset
ErrorGain
RangeInput
Data
C
+
⎟
⎠
⎞
⎜
⎝
⎛
+
××
−
=
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
12-BIT CDC RESULT
BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
DATA HIGHMSB DATA LO
W
LSB
BIT 1 BIT 0
0
07726-044
Figure 36. CDC Data Register
Table 8. AD7156 Capacitance-to-Data Mapping
1
Data Input Capacitance
0x0000 Under range (below 0 pF)
0x3000 Zero scale (0 pF)
0x5800 Quarter scale (+0.5 pF)—auto-DAC step down
0x8000 Midscale (+1 pF)
0xA800 Three-quarter scale (+1.5 pF)—auto-DAC step up
0xD000 Full scale (+2 pF)
0xFFF0 Over range (above +2 pF)
1
An ideal part with no offset and gain error, values shown in picofarad for 2 pF capacitance input range.