Datasheet

AD7152/AD7153
Rev. 0 | Page 3 of 24
SPECIFICATIONS
V
DD
= 2.7 V to 3.6 V; GND = 0 V; −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit
1
Test Conditions/Comments
CAPACITIVE INPUT
Capacitive Input Ranges ±2 pF Differential mode
±1 pF
±0.5 pF
±0.25 pF
4 pF Single-ended mode
2 pF
1 pF
0.5 pF
Gain Matching Between Ranges ±3 % of FS
Integral Nonlinearity (INL)
2
±0.05 % of FS
No Missing Codes
2
12 Bits
Resolution, p-p
2, 3
10 Bits 25°C, V
DD
= 3.3 V, 4 pF range
Resolution Effective
2, 3
12 Bits 25°C, V
DD
= 3.3 V, 4 pF range
Absolute Error
4
±20 fF
25°C, V
DD
= 3.3 V, after system offset
calibration, ±2 pF range
System Offset Calibration Range
5, 6
40 % of FSR
Offset Deviation over Temperature
2
1 5 fF
Single-ended mode, CIN and EXC
pins disconnected, see Figure 8
0.3 1 fF
Differential mode, CIN and EXC
pins disconnected
Gain Error
7
0.5 % of FSR 25°C, V
DD
= 3.3 V
Gain Deviation over Temperature
2
0.3 0.4 % of FSR See Figure 7
Allowed Capacitance, CIN to GND
2
50 pF See Figure 9 and Figure 10
Allowed Resistance, CIN to GND
2
10 See Figure 13
Allowed Serial Resistance
2
20 See Figure 16
Power Supply Rejection DC 2 fF/V See Figure 17
Normal-Mode Rejection
2
−70 dB 50 Hz ± 1 Hz, conversion time = 60 ms
−70 dB 60 Hz ± 1 Hz, conversion time = 50 ms
Channel-to-Channel Isolation
2
−70 dB AD7152 only
CAPDAC
Full Range 5 6.25 pF
Resolution
8
200 fF 5-bit CAPDAC
Differential Nonlinearity (DNL)
2
0.25 LSB See Figure 18 and Figure 19
Offset Deviation over Temperature
2
0.3 % of CAPDAC FSR Single-ended mode
EXCITATION
Frequency 30.9 32 32.8 kHz
Voltage ±V
DD
/2 V
Allowed Capacitance, EXC to GND
2
300 pF See Figure 11 and Figure 12
SERIAL INTERFACE LOGIC INPUTS (SCL, SDA)
Input High Voltage, V
IH
1.5 V
Input Low Voltage, V
IL
0.8 V
Input Leakage Current (SCL) ±0.1 ±5 μA
OPEN-DRAIN OUTPUT (SDA)
Output Low Voltage, V
OL
0.4 V
I
SINK
= 6.0 mA
Output High Leakage Current, I
OH
0.1 5 μA V
OUT
= V
DD
POWER SUPPLY MONITOR
Threshold Voltage, V
DD
2.45 2.65 V