Datasheet

AD7152/AD7153
Rev. 0 | Page 20 of 24
DIFFERENTIAL CAPACITIVE INPUT
When configured for differential mode (the CAPDIFF bit in the
Channel 1 Setup or Channel 2 Setup registers is set to 1), the
CDC measures the difference between positive and negative
capacitance input.
Each of the two input capacitances, C
X
and C
Y
, between the
EXC and CIN pins must be less than 2 pF (without using the
CAPDACs) or must be less than 9 pF and balanced by the
CAPDACs. Balancing by the CAPDACs means that both
C
X
− CAPDAC(+) and C
Y
− CAPDAC(−) are less than 2 pF.
If the unbalanced capacitance between the EXC and CIN pins
is higher than 2 pF, the CDC introduces a gain error, an offset
error, and nonlinearity error (see Figure 32, Figure 33, and
Figure 34).
0x0000 ... 0xFFF0
DATA
CAPDIFF = 1
±2pF
CDC
EXC
CIN(+)
CIN(–)
C
X
0pF TO 4pF
C
Y
0pF TO 4pF
CAPDAC(+)
OFF
CAPDAC(–)
OFF
07450-020
Figure 32. CDC Differential Input Mode
0x0000 ... 0xFFF0
DATA
CAPDIFF = 1
±2pF
CDC
EXC
CIN(+)
CIN(–)
C
X
4pF TO 6pF
(5 ± 1pF)
C
Y
4pF TO 6pF
(5 ± 1pF)
CAPDAC(+)
5pF
CAPDAC(–)
5pF
07450-021
Figure 33. Using CAPDAC in Differential Mode
0x0000 ... 0xFFF0
DATA
CAPDIFF = 1
±2pF
CDC
EXC
CIN(+)
CIN(–)
C
X
3pF TO 7pF
(5 ± 2pF)
C
Y
5pF
CAPDAC(+)
5pF
CAPDAC(–)
5pF
07450-121
Figure 34. Using CAPDAC in Differential Mode
PARASITIC CAPACITANCE TO GROUND
DATA
CDC
EXC
C
GND1
CIN
C
GND2
C
X
07450-012
Figure 35. Parasitic Capacitance to Ground
The CDC architecture used in the AD7152/AD7153 measures
C
X
connected between the EXC pin and the CIN pin. In theory,
any capacitance, C
GND
, to ground should not affect the CDC
result (see Figure 35).
The practical implementation of the circuitry in the chip
implies certain limits and the result is gradually affected by
capacitance to ground. See the allowed capacitance to GND
in the Specifications table and, Figure 9 through Figure 12.
PARASITIC RESISTANCE TO GROUND
DATA
CDC
EXC
R
GND1
CIN
R
GND2
C
X
07450-013
Figure 36. Parasitic Resistance to Ground
The CDC result can be affected by a leakage current from
the C
X
to ground; therefore, the C
X
should be isolated from
the ground. The influence of the leakage current varies with
the power supply voltage (see Figure 36).
A higher leakage current to ground results in a gain error,
an offset error, and a nonlinearity error (see Figure 13 and
Figure 14).