Datasheet

AD7151
Rev. 0 | Page 18 of 28
SETUP REGISTER
Address Pointer 0x0B
8 Bits, Read/Write, Factory Preset 0x0B
Table 10. Setup Register Bit Map
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic RngH RngL –
Hyst
ThrSettling (4-Bit Value)
Default 0 0 0 0 0x0B
Table 11. Setup Register Bit Descriptions
Bit Mnemonic Description
Range bits set the CDC input range and determine the step for the AutoDAC function.
RngH RngL Capacitive Input Range (pF) AutoDAC Step (CAPDAC LSB)
0 0 2 4
0 1 0.5 1
1 0 1 2
7
6
RngH
RngL
1 1 4 8
5 – This bit should be 0 for the specified operation.
4
Hyst Hyst = 1 disables hysteresis in adaptive threshold mode. This bit has no effect in fixed threshold mode;
hysteresis is always disabled in the fixed threshold mode.
3
2
1
0
ThrSettling
Determines the settling time constant of the data average and thus the settling time of the adaptive
thresholds.
The response of the average to an input capacitance step change (that is, response to the change in the CDC
output data) is an exponential settling curve characterized by the following equation:
)1()0()(
/ TimeConstN
eChangeAverageNAverage −+=
where:
Average(N) is the value of average N complete CDC conversion cycles after a step change on the input
Average(0) is the value before the step change
TimeConst can be selected in the range between 2 and 65,536 conversion cycle multiples, in steps of power of
2, by programming the ThrSettling bits.
)1(
2
+
=
gThrSettlin
TimeConst
See
Figure 39.
INPUT CAPACITANCE
(CDC DATA) CHANGE
DATA AVERAGE RESPONSE
TIME
07086-028
Figure 39. Data Average Response to Data Step Change