Datasheet

AD7142
Rev. A | Page 7 of 72
I
2
C TIMING SPECIFICATIONS (AD7142-1)
T
A
= −40°C to +85°C; V
DRIVE
= 1.65 V to 3.6 V; AV
CC
, DV
CC
= 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure
compliance. All input signals timed from a voltage level of 1.6 V.
Table 5. I
2
C Timing Specifications
1
Parameter Limit Unit Description
f
SCLK
400 kHz max
t
1
0.6 μs min Start condition hold time, t
HD; STA
t
2
1.3 μs min Clock low period, t
LOW
t
3
0.6 μs min Clock high period, t
HIGH
t
4
100 ns min Data setup time, t
SU; DAT
t
5
300 ns min Data hold time, t
HD; DAT
t
6
0.6 μs min Stop condition setup time, t
SU; STO
t
7
0.6 μs min Start condition setup time, t
SU; STA
t
8
1.3 μs min Bus free time between stop and start conditions, t
BUF
t
R
300 ns max Clock/data rise time
t
F
300 ns max Clock/data fall time
1
Guaranteed by design, not production tested.
05702-003
SCLK
SDATA
t
R
t
F
t
2
t
5
t
1
t
3
t
4
STOP START STOPSTART
t
7
t
6
t
1
t
8
Figure 4. I
2
C Detailed Timing Diagram