Datasheet

AD7142
Rev. A | Page 6 of 72
SPI TIMING SPECIFICATIONS (AD7142)
T
A
= −40°C to +85°C; V
DRIVE
= 1.65 V to 3.6 V; AV
CC
, DV
CC
= 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure
compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.6 V.
Table 4. SPI Timing Specifications
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
5 MHz max
t
1
5 ns min
CS falling edge to first SCLK falling edge
t
2
20 ns min SCLK high pulse width
t
3
20 ns min SCLK low pulse width
t
4
15 ns min SDI setup time
t
5
15 ns min SDI hold time
t
6
20 ns max SDO access time after SCLK falling edge
t
7
16 ns max
CS rising edge to SDO high impedance
t
8
15 ns min
SCLK rising edge to
CS high
CS
SCL
K
SDI
SDO
t
1
116
15
MSB
LSB
23
MSB
LSB
12
15
16
t
2
t
4
t
5
t
3
t
6
t
7
t
8
05702-002
Figure 3. SPI Detailed Timing Diagram