Datasheet

AD7142
Rev. A | Page 45 of 72
Table 26. STAGE_COMPLETE_INT_EN Register
Address Data Bit Default Value Type Name Description
0x007 [0] 0 R/W STAGE0_COMPLETE_EN STAGE0 conversion interrupt control
0 = interrupt source disabled
1 =
INT asserted at completion of STAGE0 conversion
[1] 0 STAGE1_COMPLETE_EN STAGE1 conversion interrupt control
0 = interrupt source disabled
1 =
INT asserted at completion of STAGE1 conversion
[2] 0 STAGE2_COMPLETE_EN STAGE2 conversion interrupt control
0 = interrupt source disabled
1 =
INT asserted at completion of STAGE2 conversion
[3] 0 STAGE3_COMPLETE_EN STAGE3 conversion interrupt control
0 = interrupt source disabled
1 =
INT asserted at completion of STAGE3 conversion
[4] 0 STAGE4_COMPLETE_EN STAGE4 conversion interrupt control
0 = interrupt source disabled
1 =
INT asserted at completion of STAGE4 conversion
[5] 0 STAGE5_COMPLETE_EN STAGE5 conversion interrupt control
0 = interrupt source disabled
1 =
INT asserted at completion of STAGE5 conversion
[6] 0 STAGE6_COMPLETE_EN STAGE6 conversion interrupt control
0 = interrupt source disabled
1 =
INT asserted at completion of STAGE6 conversion
[7] 0 STAGE7_COMPLETE_EN STAGE7 conversion interrupt control
0 = interrupt source disabled
1 =
INT asserted at completion of STAGE7 conversion
[8] 0 STAGE8_COMPLETE_EN STAGE8 conversion complete interrupt control
0 = interrupt source disabled
1 =
INT asserted at completion of STAGE8 conversion
[9] 0 STAGE9_COMPLETE_EN STAGE9 conversion interrupt control
0 = interrupt source disabled
1 =
INT asserted at completion of STAGE9 conversion
[10] 0 STAGE10_COMPLETE_EN STAGE10 conversion interrupt control
0 = interrupt source disabled
1 =
INT asserted at completion of STAGE10 conversion
[11] 0 STAGE11_COMPLETE_EN STAGE11 conversion interrupt control
0 = interrupt source disabled
1 =
INT asserted at completion of STAGE11 conversion
[12] 0 GPIO_INT_EN Interrupt control when GPIO input pin changes level
0 = disabled
1 = enabled
[15:13] Unused Set unused register bits = 0