Datasheet
AD7142
Rev. A | Page 31 of 72
SERIAL INTERFACE
The AD7142 is available with an SPI serial interface. The
AD7142-1 is available with an I
2
C-compatible interface. Both
parts are the same, with the exception of the serial interface.
SPI INTERFACE
The AD7142 has a 4-wire serial peripheral interface (SPI). The
SPI has a data input pin (SDI) for inputting data to the device, a
data output pin (SDO) for reading data back from the device,
and a data clock pin (SCLK) for clocking data into and out of
the device. A chip select pin (
CS
) enables or disables the serial
interface.
CS
is required for correct operation of the SPI
interface. Data is clocked out of the AD7142 on the negative
edge of SCLK, and data is clocked into the device on the
positive edge of SCLK.
SPI Command Word
All data transactions on the SPI bus begin with the master
taking
CS
from high to low and sending out the command
word. This indicates to the AD7142 whether the transaction is a
read or a write, and gives the address of the register from which
to begin the data transfer. The following bit map shows the SPI
command word.
MSB
LSB
15 14 13 12 11 10 9:0
1 1 1 0 0
R/
W
Register address
Bits[15:11] of the command word must be set to 11100 to
successfully begin a bus transaction.
Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates a
write.
Bits[9:0] contain the target register address. When reading or
writing to more than one register, this address indicates the
address of the first register to be written to or read from.
Writing Data
Data is written to the AD7142 in 16-bit words. The first word
written to the device is the command word, with the read/write
bit set to 0. The master then supplies the 16-bit input data-word
on the SDI line. The AD7142 clocks the data into the register
addressed in the command word. If there is more than one
word of data to be clocked in, the AD7142 automatically incre-
ments the address pointer, and clocks the next data-word into
the next register.
The AD7142 continues to clock in data on the SDI line until
either the master finishes the write transition by pulling
CS
high, or the address pointer reaches its maximum value. The
AD7142 address pointer does not wrap around. When it
reaches its maximum value, any data provided by the master on
the SDI line is ignored by the AD7142.
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR CONTROL WORD AND 16 BITS FOR DATA.
3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)
CW
11
CW
10
CW
13
CW
12
SDI
CW
15
CW
14
CW
9
CW
7
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
D2 D1 D0
CW
8
t
1
t
4
16-BIT COMMAND WORD
16-BIT DATA
5 326 7 8 9 10 11 12 13 14 15 16 30 31
t
8
t
5
SCLK
1234
D15 D14 D13
17 18 19
CS
ENABLE WORD R/W REGISTER ADDRESS
t
2
t
3
05702-033
Figure 46. Single Register Write SPI Timing