Datasheet

AD7142
Rev. A | Page 28 of 72
GPIO INT OUTPUT CONTROL
The
INT
output signal can be controlled by the GPIO pin when
the GPIO is configured as an input. The GPIO is configured as
an input by setting the GPIO_SETUP bits in the interrupt
configuration register to 01. See the
GPIO section for more
information on how to configure the GPIO.
Enable the GPIO interrupt by setting the GPIO_INT_EN bit in
Register 0x007 to 1, or disable the GPIO interrupt by clearing this
bit to 0. The GPIO status bit in the conversion complete interrupt
status register reflects the status of the GPIO interrupt. This bit is
set to 1 when the GPIO has triggered
INT
. The bit is cleared on
readback from the register, provided the condition that caused
the interrupt has gone away.
The GPIO interrupt can be set to trigger on a rising edge, falling
edge, high level, or low level at the GPIO input pin.
Tabl e 14
shows how the settings of the GPIO_INPUT_CONFIG bits in
the interrupt enable register affect the behavior of
INT
.
Figure 41 to Figure 44 show how the interrupt output is cleared on
a read from the CDC conversion complete interrupt status register.
GPIO
INPUT
INT
OUTPUT
SERIAL
READBACK
GPIO
INPUT
INT
OUTPUT
1
NOTES
1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT.
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
05702-028
Figure 41.
INT
Output Controlled by the GPIO Input Example,
GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 00
GPIO
INPUT
INT
OUTPUT
SERIAL
READBACK
GPIO
INPUT
INT
OUTPUT
1
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
NOTES
1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT.
05702-029
Figure 42.
INT
Output Controlled by the GPIO Input Example,
GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 01